From patchwork Thu Feb 6 23:42:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 3598831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BF48B9F2E9 for ; Thu, 6 Feb 2014 23:49:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05BF420120 for ; Thu, 6 Feb 2014 23:49:22 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09E7620145 for ; Thu, 6 Feb 2014 23:49:21 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBYeO-0000sw-RE; Thu, 06 Feb 2014 23:46:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBYdS-0006ca-1k; Thu, 06 Feb 2014 23:45:34 +0000 Received: from vps0.lunn.ch ([178.209.37.122]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBYcV-0006Ud-Oq for linux-arm-kernel@lists.infradead.org; Thu, 06 Feb 2014 23:44:36 +0000 Received: from lunn by vps0.lunn.ch with local (Exim 4.80) (envelope-from ) id 1WBYaK-0003sD-FZ; Fri, 07 Feb 2014 00:42:20 +0100 From: Andrew Lunn To: Jason Cooper , Sebastian Hesselbarth , Gregory Clement Subject: [PATCH 12/21] ARM: Fix MULTI_TLB for feroceon Date: Fri, 7 Feb 2014 00:42:08 +0100 Message-Id: <1391730137-14814-13-git-send-email-andrew@lunn.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1391730137-14814-1-git-send-email-andrew@lunn.ch> References: <1391730137-14814-1-git-send-email-andrew@lunn.ch> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140206_184435_976636_41D95B91 X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.4 (--) Cc: Andrew Lunn , linux ARM X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Feroceon has the same flush operations as v4wbi, but has an additional flag, TLB_L2CLEAN_FR. When building with MULTI_TLB this flag is placed into cpu_tlb.tlb_flags, so there needs to be a cpu_tlb specifically for feroceon, rather than sharing the v4wbi. Signed-off-by: Andrew Lunn --- arch/arm/mm/proc-feroceon.S | 2 +- arch/arm/mm/tlb-v4wbi.S | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index db79b62c92fb..b76c2706cb02 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -607,7 +607,7 @@ __\name\()_proc_info: .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP .long \cpu_name .long feroceon_processor_functions - .long v4wbi_tlb_fns + .long fr_tlb_fns .long feroceon_user_fns .long \cache .size __\name\()_proc_info, . - __\name\()_proc_info diff --git a/arch/arm/mm/tlb-v4wbi.S b/arch/arm/mm/tlb-v4wbi.S index 1f6062b6c1c1..4e053fef3487 100644 --- a/arch/arm/mm/tlb-v4wbi.S +++ b/arch/arm/mm/tlb-v4wbi.S @@ -28,6 +28,7 @@ * - mm - mm_struct describing address space */ .align 5 +ENTRY(fr_flush_user_tlb_range) ENTRY(v4wbi_flush_user_tlb_range) vma_vm_mm ip, r2 act_mm r3 @ get current->active_mm @@ -46,6 +47,7 @@ ENTRY(v4wbi_flush_user_tlb_range) blo 1b mov pc, lr +ENTRY(fr_flush_kern_tlb_range) ENTRY(v4wbi_flush_kern_tlb_range) mov r3, #0 mcr p15, 0, r3, c7, c10, 4 @ drain WB @@ -62,3 +64,4 @@ ENTRY(v4wbi_flush_kern_tlb_range) /* define struct cpu_tlb_fns (see and proc-macros.S) */ define_tlb_functions v4wbi, v4wbi_tlb_flags + define_tlb_functions fr, fr_tlb_flags