From patchwork Tue Feb 11 02:15:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarek Dakhran X-Patchwork-Id: 3624621 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1E3959F2D6 for ; Tue, 11 Feb 2014 02:18:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 377F3201F7 for ; Tue, 11 Feb 2014 02:18:50 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36DEC201F0 for ; Tue, 11 Feb 2014 02:18:49 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WD2vq-0006hi-LI; Tue, 11 Feb 2014 02:18:42 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WD2vn-0004Wn-L5; Tue, 11 Feb 2014 02:18:39 +0000 Received: from mailout2.w1.samsung.com ([210.118.77.12]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WD2vj-0004W4-W2 for linux-arm-kernel@lists.infradead.org; Tue, 11 Feb 2014 02:18:37 +0000 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N0T005II7Q6RU40@mailout2.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 11 Feb 2014 02:18:06 +0000 (GMT) X-AuditID: cbfec7f5-b7fc96d000004885-18-52f988629bff Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 87.53.18565.26889F25; Tue, 11 Feb 2014 02:18:10 +0000 (GMT) Received: from localhost.localdomain ([168.219.243.98]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0N0T00D507PV2M00@eusync1.samsung.com>; Tue, 11 Feb 2014 02:18:10 +0000 (GMT) From: Tarek Dakhran To: linux-kernel@vger.kernel.org Subject: [PATCH v1 1/1] ARM: EXYNOS: enable boot all secondary cpus instead 2 Date: Tue, 11 Feb 2014 11:15:29 +0900 Message-id: <1392084929-14116-2-git-send-email-t.dakhran@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1392084929-14116-1-git-send-email-t.dakhran@samsung.com> References: <1392084929-14116-1-git-send-email-t.dakhran@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsVy+t/xy7pJHT+DDN5t5bGYtO4Ak8XD9TdZ LPrfLGS1OPdqJaNF74KrbBabHl9jtbi8aw6bxYzz+5gsbl/mtVh6/SKTxYTpa1ksWvceYbf4 3fOJ2WL981OMFutnvGaxmDrjB7uDgMeaeWsYPVqae9g8Lvf1Mnn8XfWC2WPnrLvsHiuXf2Hz 2LSqk83jzrU9bB6bl9R79G1ZxejxeZNcAHcUl01Kak5mWWqRvl0CV8bbTb9YCz4qVny6o9PA uFG6i5GTQ0LAROLCo3+sELaYxIV769lAbCGBpYwSL9vcIexeJomGuYFdjBwcbALaElt2eIGE RQQUJDb3PgNrZRY4xiKxaEo+iC0s4Cux7FI/E4jNIqAqMf/hF7CRvAKuEoemTGeEWKUo0f1s AlicU8BNYvmZhVBrXSXOHNvFPIGRdwEjwypG0dTS5ILipPRcI73ixNzi0rx0veT83E2MkAD/ uoNx6TGrQ4wCHIxKPLwaX38ECbEmlhVX5h5ilOBgVhLhPWv3M0iINyWxsiq1KD++qDQntfgQ IxMHp1QDI/Nu8VL5Ky3ickmlS9rlrq06M+uzSMel2gB3zqb7x7q7ZF/6yUzQXHskrGNRv6WV ls1ugwUamg+LJnVM11tjVM9/+0qi983txacsSk7Xz4n8KcLfuE9WJE7lzNP/V3w/ZUdbiKyL fc8UcCth2RVmsWW/dpzWYtog3/LFosXZYVdJmtLWJT8blViKMxINtZiLihMBrPpggE4CAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140210_211836_182028_BAAEB2AF X-CRM114-Status: GOOD ( 16.19 ) X-Spam-Score: -4.5 (----) Cc: Mark Rutland , Tarek Dakhran , Kukjin Kim , Russell King , Pawel Moll , Ian Campbell , Tomasz Figa , Chander Kashyap , linux-samsung-soc@vger.kernel.org, Rob Herring , Vyacheslav Tyrtov , Ben Dooks , Kumar Gala , Tarek Dakhran , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Functions to boot secondary cpus added. exynos_core_power_up(unsigned int cpu) added for power up any cpu. exynos_core_power_down(unsigned int cpu) for power down any cpu. Signed-off-by: Tarek Dakhran --- arch/arm/mach-exynos/hotplug.c | 11 ++++-- arch/arm/mach-exynos/platsmp.c | 75 ++++++++++++++++++++++++++++----------- arch/arm/mach-exynos/regs-pmu.h | 5 +++ 3 files changed, 68 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 5eead53..71982fa 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -90,13 +90,18 @@ static inline void cpu_leave_lowpower(void) : "cc"); } +static void exynos_core_power_down(unsigned int cpu) +{ + writel_relaxed(0, S5P_ARM_CORE_CONFIGURATION(cpu)); +} + static inline void platform_do_lowpower(unsigned int cpu, int *spurious) { for (;;) { - /* make cpu1 to be turned off at next WFI command */ - if (cpu == 1) - __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION); + /* make cpu to be turned off at next WFI command */ + if (cpu) + exynos_core_power_down(cpu); /* * here's the WFI diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 8ea02f6..4008fc8 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -88,10 +88,61 @@ static void exynos_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } +/* + * core_power_state is used to get core power state. + * returns: + * 0x0 - powered off; + * 0x3 - powered on; + * other values - in process; + */ +static unsigned int core_power_state(unsigned int cpu) +{ + unsigned int status = readl_relaxed(S5P_ARM_CORE_STATUS(cpu)); + + return status & CORE_PWR_STATE_MASK; +} + +#define TIMEOUT 10 +#define DELAY_TIME 1 + +static int wait_core_power_up(unsigned int cpu) +{ + int timeout = TIMEOUT; + + do { + /* checking if power controller in reset */ + if (core_power_state(cpu) == S5P_CORE_LOCAL_PWR_EN) + return 0; + mdelay(DELAY_TIME); + timeout -= DELAY_TIME; + } while (timeout > 0); + + return -ETIMEDOUT; /* timeout */ +} + +static int exynos_core_power_up(unsigned int cpu) +{ + int ret; + + if (core_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) { + writel_relaxed(S5P_CORE_LOCAL_PWR_EN, + S5P_ARM_CORE_CONFIGURATION(cpu)); + + ret = wait_core_power_up(cpu); + if (ret) { + pr_debug("timeout powering on CPU%d\n", cpu); + return ret; /* timeout */ + } + } + + return 0; +} + static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; unsigned long phys_cpu = cpu_logical_map(cpu); + int ret; /* * Set synchronisation state between this boot processor @@ -109,26 +160,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(phys_cpu); - if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { - __raw_writel(S5P_CORE_LOCAL_PWR_EN, - S5P_ARM_CORE1_CONFIGURATION); - - timeout = 10; - - /* wait max 10 ms until cpu1 is on */ - while ((__raw_readl(S5P_ARM_CORE1_STATUS) - & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { - if (timeout-- == 0) - break; - - mdelay(1); - } - - if (timeout == 0) { - printk(KERN_ERR "cpu1 power enable failed"); - spin_unlock(&boot_lock); - return -ETIMEDOUT; - } + ret = exynos_core_power_up(cpu); + if (ret) { + spin_unlock(&boot_lock); + return ret; } /* * Send the secondary CPU a soft interrupt, thereby causing diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 7c029ce..4fc1e8f 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -104,6 +104,11 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) +#define CORE_PWR_STATE_MASK 0x3 + +#define S5P_ARM_CORE_CONFIGURATION(_nr) (S5P_PMUREG(0x2000) + ((_nr) * 0x80)) +#define S5P_ARM_CORE_STATUS(_nr) (S5P_PMUREG(0x2004) + ((_nr) * 0x80)) + #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)