From patchwork Wed Feb 12 10:45:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 3636751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 008E7BF13A for ; Wed, 12 Feb 2014 10:46:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CAA62201CD for ; Wed, 12 Feb 2014 10:46:57 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A99B620149 for ; Wed, 12 Feb 2014 10:46:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WDXL9-00027Z-TO; Wed, 12 Feb 2014 10:46:52 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WDXL7-00063b-E4; Wed, 12 Feb 2014 10:46:49 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WDXL3-00062h-QY for linux-arm-kernel@lists.infradead.org; Wed, 12 Feb 2014 10:46:47 +0000 Received: from dude.hi.pengutronix.de ([10.1.0.7] helo=dude.pengutronix.de) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1WDXK9-0006Op-Ex; Wed, 12 Feb 2014 11:45:49 +0100 From: Lucas Stach To: Shawn Guo Subject: [PATCH] ARM: imx6: fix !CONFIG_PM and !CONFIG_CPU_IDLE build Date: Wed, 12 Feb 2014 11:45:48 +0100 Message-Id: <1392201948-16311-1-git-send-email-l.stach@pengutronix.de> X-Mailer: git-send-email 1.8.5.3 X-SA-Exim-Connect-IP: 10.1.0.7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140212_054646_338900_15B55CC8 X-CRM114-Status: GOOD ( 18.28 ) X-Spam-Score: -2.6 (--) Cc: linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When building a kernel with only CONFIG_CPU_IDLE, but no CONFIG_PM we still need the functions to set the lpm mode and chicken bits. Also if both options are unset, we have to stub out the set_lpm function, as this one is called from the clk driver directly. Signed-off-by: Lucas Stach --- This fix depends on an earlier one by Philipp: "ARM: imx6: Initialize low-power mode early again" Both should go to stable after a sensible sinking time. --- arch/arm/mach-imx/Makefile | 9 +++- arch/arm/mach-imx/common.h | 11 +++-- arch/arm/mach-imx/pm-imx6q.c | 112 ++++++++++++++++++++++--------------------- 3 files changed, 72 insertions(+), 60 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index befcaf5d0574..a8f2a1a1cbfc 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -102,9 +102,14 @@ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o +obj-$(CONFIG_SOC_IMX6Q) += headsmp.o # i.MX6SL reuses i.MX6Q code -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o +obj-$(CONFIG_SOC_IMX6SL) += headsmp.o +endif + +ifeq ($(findstring y,$(CONFIG_CPU_IDLE) $(CONFIG_PM)),y) +obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o endif # i.MX5 based machines diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 59c3b9b26bb4..9141277e143f 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -138,7 +138,6 @@ void imx_gpc_irq_unmask(struct irq_data *d); void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); void imx6q_set_chicken_bit(void); void imx_cpu_die(unsigned int cpu); @@ -146,14 +145,20 @@ int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_PM void imx6q_pm_init(void); -void imx6q_pm_set_ccm_base(void __iomem *base); void imx5_pm_init(void); #else static inline void imx6q_pm_init(void) {} -static inline void imx6q_pm_set_ccm_base(void __iomem *base) {} static inline void imx5_pm_init(void) {} #endif +#if defined(CONFIG_PM) || defined(CONFIG_CPU_IDLE) +void imx6q_pm_set_ccm_base(void __iomem *base); +int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); +#else +static inline void imx6q_pm_set_ccm_base(void __iomem *base) {} +static inline int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { return 0; } +#endif + #ifdef CONFIG_NEON int mx51_neon_fixup(void); #else diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 7a9b98589db7..038091050e61 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -68,56 +68,6 @@ void imx6q_set_chicken_bit(void) writel_relaxed(val, ccm_base + CGPR); } -static void imx6q_enable_rbc(bool enable) -{ - u32 val; - - /* - * need to mask all interrupts in GPC before - * operating RBC configurations - */ - imx_gpc_mask_all(); - - /* configure RBC enable bit */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_EN; - val |= enable ? BM_CCR_RBC_EN : 0; - writel_relaxed(val, ccm_base + CCR); - - /* configure RBC count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_BYPASS_COUNT; - val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; - writel(val, ccm_base + CCR); - - /* - * need to delay at least 2 cycles of CKIL(32K) - * due to hardware design requirement, which is - * ~61us, here we use 65us for safe - */ - udelay(65); - - /* restore GPC interrupt mask settings */ - imx_gpc_restore_all(); -} - -static void imx6q_enable_wb(bool enable) -{ - u32 val; - - /* configure well bias enable bit */ - val = readl_relaxed(ccm_base + CLPCR); - val &= ~BM_CLPCR_WB_PER_AT_LPM; - val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; - writel_relaxed(val, ccm_base + CLPCR); - - /* configure well bias count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_WB_COUNT; - val |= enable ? BM_CCR_WB_COUNT : 0; - writel_relaxed(val, ccm_base + CCR); -} - int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { struct irq_desc *iomuxc_irq_desc; @@ -175,6 +125,62 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) return 0; } +void __init imx6q_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + +#ifdef CONFIG_PM +static void imx6q_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpc_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_EN; + val |= enable ? BM_CCR_RBC_EN : 0; + writel_relaxed(val, ccm_base + CCR); + + /* configure RBC count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_BYPASS_COUNT; + val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; + writel(val, ccm_base + CCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpc_restore_all(); +} + +static void imx6q_enable_wb(bool enable) +{ + u32 val; + + /* configure well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configure well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); +} + static int imx6q_suspend_finish(unsigned long val) { cpu_do_idle(); @@ -213,11 +219,6 @@ static const struct platform_suspend_ops imx6q_pm_ops = { .valid = suspend_valid_only_mem, }; -void __init imx6q_pm_set_ccm_base(void __iomem *base) -{ - ccm_base = base; -} - void __init imx6q_pm_init(void) { struct regmap *gpr; @@ -239,3 +240,4 @@ void __init imx6q_pm_init(void) suspend_set_ops(&imx6q_pm_ops); } +#endif