From patchwork Wed Feb 19 21:11:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3683111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A4417BF13A for ; Wed, 19 Feb 2014 21:15:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B7417201BA for ; Wed, 19 Feb 2014 21:14:59 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8732720155 for ; Wed, 19 Feb 2014 21:14:58 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGETJ-0001xe-Uq; Wed, 19 Feb 2014 21:14:26 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGETC-0000EI-8M; Wed, 19 Feb 2014 21:14:18 +0000 Received: from mail-bl2on0123.outbound.protection.outlook.com ([65.55.169.123] helo=na01-bl2-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGET1-0000D5-VC for linux-arm-kernel@lists.infradead.org; Wed, 19 Feb 2014 21:14:09 +0000 Received: from BL2FFO11FD027.protection.gbl (10.173.160.33) by BL2FFO11HUB043.protection.gbl (10.173.161.119) with Microsoft SMTP Server (TLS) id 15.0.868.13; Wed, 19 Feb 2014 21:13:33 +0000 Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by BL2FFO11FD027.mail.protection.outlook.com (10.173.161.106) with Microsoft SMTP Server (TLS) id 15.0.868.13 via Frontend Transport; Wed, 19 Feb 2014 21:13:33 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.342.0; Wed, 19 Feb 2014 13:00:53 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s1JLDRWF004935; Wed, 19 Feb 2014 13:13:30 -0800 (PST) From: To: Subject: [PATCH 2/3] clk: socfpga: Support multiple parents for the pll clocks Date: Wed, 19 Feb 2014 15:11:11 -0600 Message-ID: <1392844273-11918-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392844273-11918-1-git-send-email-dinguyen@altera.com> References: <1392844273-11918-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019001)(6009001)(199002)(189002)(74706001)(56776001)(19580395003)(76482001)(59766001)(77982001)(77096001)(81686001)(79102001)(20776003)(50466002)(88136002)(74876001)(83322001)(51856001)(76786001)(44976005)(19580405001)(36756003)(77156001)(63696002)(53416003)(76796001)(6806004)(46102001)(86362001)(93916002)(93516002)(80976001)(81816001)(31966008)(47776003)(94316002)(90146001)(86152002)(53806001)(33646001)(92566001)(87266001)(50226001)(95416001)(65816001)(80022001)(87286001)(47446002)(95666001)(69226001)(85306002)(87936001)(93136001)(62966002)(47736001)(54316002)(81542001)(83072002)(85852003)(74662001)(49866001)(4396001)(47976001)(50986001)(74366001)(81342001)(89996001)(48376002)(94946001)(74502001)(92726001)(56816005); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2FFO11HUB043; H:SJ-ITEXEDGE02.altera.priv.altera.com; CLIP:66.35.236.232; FPR:6839F545.28C49E0B.ECDD1A46.9C5C764A.20261; MLV:nspm; InfoDomainNonexistentA:1; MX:1; LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 012792EC17 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140219_161408_146171_D276BAEF X-CRM114-Status: GOOD ( 11.70 ) X-Spam-Score: -1.9 (-) Cc: Mike Turquette , Steffen Trumtrar , dinh.linux@gmail.com, Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen Cc: Mike Turquette Cc: Steffen Trumtrar --- drivers/clk/socfpga/clk-pll.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index 834b6e9..88dafb5 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -38,6 +38,9 @@ #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 #define SOCFPGA_PLL_DIVQ_SHIFT 16 +#define CLK_MGR_PLL_CLK_SRC_SHIFT 22 +#define CLK_MGR_PLL_CLK_SRC_MASK 0x3 + #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, @@ -60,8 +63,19 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, return (unsigned long)vco_freq; } +static u8 clk_pll_get_parent(struct clk_hw *hwclk) +{ + u32 pll_src; + struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); + + pll_src = readl(socfpgaclk->hw.reg); + return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) & + CLK_MGR_PLL_CLK_SRC_MASK; +} + static struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, + .get_parent = clk_pll_get_parent, }; static __init struct clk *__socfpga_pll_init(struct device_node *node, @@ -71,9 +85,10 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, struct clk *clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; - const char *parent_name; + const char *parent_name[SOCFPGA_MAX_PARENTS]; struct clk_init_data init; int rc; + int i = 0; of_property_read_u32(node, "reg", ®); @@ -88,10 +103,13 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, init.name = clk_name; init.ops = ops; init.flags = 0; - parent_name = of_clk_get_parent_name(node, 0); - init.parent_names = parent_name ? &parent_name : NULL; - init.num_parents = parent_name ? 1 : 0; + while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] = + of_clk_get_parent_name(node, i)) != NULL) + i++; + + init.num_parents = i; + init.parent_names = parent_name; pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;