From patchwork Thu Feb 20 17:42:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 3689121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 500F49F35F for ; Thu, 20 Feb 2014 17:48:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 69F9720149 for ; Thu, 20 Feb 2014 17:48:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 660D920145 for ; Thu, 20 Feb 2014 17:48:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGXiu-0005uL-DM; Thu, 20 Feb 2014 17:47:48 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGXe2-0007BJ-Eu; Thu, 20 Feb 2014 17:42:46 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGXdz-0007AQ-CA for linux-arm-kernel@lists.infradead.org; Thu, 20 Feb 2014 17:42:44 +0000 Received: from mudshark.cambridge.arm.com (mudshark.cambridge.arm.com [10.1.203.36]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s1KHgEki025365; Thu, 20 Feb 2014 17:42:14 GMT Received: by mudshark.cambridge.arm.com (Postfix, from userid 1000) id 07BCBC2A8A; Thu, 20 Feb 2014 17:42:10 +0000 (GMT) From: Will Deacon To: olof@lixom.net Subject: [PATCH] irqchip: gic: use dmb ishst instead of dsb when raising a softirq Date: Thu, 20 Feb 2014 17:42:07 +0000 Message-Id: <1392918127-1430-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 1.8.2.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140220_124243_664064_019C6BCE X-CRM114-Status: GOOD ( 14.14 ) X-Spam-Score: -7.5 (-------) Cc: Thomas Gleixner , arm@kernel.org, Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When sending an SGI to another CPU, we require a barrier to ensure that any pending stores to normal memory are made visible to the recipient before the interrupt arrives. Rather than use a vanilla dsb() (which will soon cause an assembly error on arm64) before the writel_relaxed, we can instead use dsb(ishst), since we just need to ensure that any pending normal writes are visible within the inner-shareable domain before we poke the GIC. With this observation, we can then further weaken the barrier to a dmb(ishst), since other CPUs in the inner-shareable domain must observe the write to the distributor before the SGI is generated. Cc: Thomas Gleixner Acked-by: Marc Zyngier Acked-by: Catalin Marinas Signed-off-by: Will Deacon --- Hi Olof, Please can you take this via arm-soc for 3.15? That will let me activate the new barrier options for arm64 at the end of the next merge window (in the meantime, you can pass them but they are ignored). Cheers, Will drivers/irqchip/irq-gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 341c6016812d..500e533b9648 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -661,9 +661,9 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) /* * Ensure that stores to Normal memory are visible to the - * other CPUs before issuing the IPI. + * other CPUs before they observe us issuing the IPI. */ - dsb(); + dmb(ishst); /* this always happens on GIC0 */ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);