From patchwork Fri Feb 28 18:07:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 3743811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B812EBF13A for ; Fri, 28 Feb 2014 18:12:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DDAD8202EB for ; Fri, 28 Feb 2014 18:12:51 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6008202B4 for ; Fri, 28 Feb 2014 18:12:50 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJRu1-0004kC-ID; Fri, 28 Feb 2014 18:11:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJRtc-0000Hh-Ue; Fri, 28 Feb 2014 18:10:52 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJRt9-0000Ay-L5 for linux-arm-kernel@lists.infradead.org; Fri, 28 Feb 2014 18:10:26 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s1SI9Hkb011594; Fri, 28 Feb 2014 12:09:17 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s1SI9HtS029979; Fri, 28 Feb 2014 12:09:17 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Fri, 28 Feb 2014 12:09:17 -0600 Received: from khorivan.synapse.com (incasgf5a_e1_2.itg.ti.com [10.167.216.36]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s1SI8t4p003787; Fri, 28 Feb 2014 12:09:10 -0600 From: Ivan Khoronzhuk To: Subject: [PATCH 2/5] Power: reset: add bindings for keystone reset driver Date: Fri, 28 Feb 2014 20:07:42 +0200 Message-ID: <1393610865-23630-3-git-send-email-ivan.khoronzhuk@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393610865-23630-1-git-send-email-ivan.khoronzhuk@ti.com> References: <1393610865-23630-1-git-send-email-ivan.khoronzhuk@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140228_131023_967407_38970E43 X-CRM114-Status: UNSURE ( 7.07 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -3.8 (---) Cc: Mark Rutland , linux-doc@vger.kernel.org, catalin.marinas@arm.com, devicetree@vger.kernel.org, ldewangan@nvidia.com, anton@enomsg.org, lho@apm.com, abhimany@codeaurora.org, ksankaran@apm.com, fkan@apm.com, grygorii.strashko@ti.com, Pawel Moll , Ian Campbell , w-kwok2@ti.com, Rob Herring , linux-arm-kernel@lists.infradead.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, Rob Landley , Kumar Gala , olof@lixom.net, Ivan Khoronzhuk X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This node is intended to allow SoC reset in case of software reset or appropriate watchdogs. The Keystone SoCs can contain up to 4 watchdog timers to reset SoC. Each watchdog timer event input is connected to the Reset Mux block. The Reset Mux block can be configured to cause reset or not. Additionally soft or hard reset can be configured. Signed-off-by: Ivan Khoronzhuk --- CC: Rob Herring CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: Rob Landley .../bindings/power/reset/keystone-reset.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/keystone-reset.txt diff --git a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt new file mode 100644 index 0000000..5ad5883 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt @@ -0,0 +1,59 @@ +* Device tree bindings for Texas Instruments keystone reset + +This node is intended to allow SoC reset in case of software reset +of selected watchdogs. + +The Keystone SoCs can contain up to 4 watchdog timers to reset +SoC. Each watchdog timer event input is connected to the Reset Mux +block. The Reset Mux block can be configured to cause reset or not. + +Additionally soft or hard reset can be configured. + +Required properties: + +- compatible: ti,keystone-reset + +- reg: Contains offset/length value for mux registers. + + reg = <0x23100e4 0x10>, + <0x2620328 0x10>; + +-reg-names: Contains two ranges "pllregs" and "muxregs". + "pllregs" - PLL reset control regs: RSTYPE, RSCTRL, + RSCFG, RSISO. + "muxregs" - mux block registers for all watchdogs. + +Optional properties: + +- ti,soft-reset: Boolean option indicating soft reset. + By default hard reset is used. + +- ti,wdt_list: WDT list that can cause SoC reset. + The list in format: <0>, <2>; + Begins from 0 to 3, as keystone can contain up + to 4 SoC reset watchdogs. + +Example 1: +Setup keystone reset so that in case software reset or +WDT1 is triggered it issues hard reset for SoC. + +rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x23100e4 0x10>, + <0x2620328 0x10>; + reg-names = "pllregs", "muxregs"; + ti,wdt_list = <0>; +}; + +Example 2: +Setup keystone reset so that in case of software reset or +WDT1 or WDT3 is triggered it issues soft reset for SoC. + +rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x23100e4 0x10>, + <0x2620328 0x10>; + reg-names = "pllregs", "muxregs"; + ti,wdt_list = <0>, <2>; + ti,soft-reset; +};