From patchwork Fri Feb 28 18:07:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 3743791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 951A2BF13A for ; Fri, 28 Feb 2014 18:11:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7F0E202DD for ; Fri, 28 Feb 2014 18:11:47 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D0291202B4 for ; Fri, 28 Feb 2014 18:11:46 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJRtW-0004TQ-0r; Fri, 28 Feb 2014 18:10:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJRtJ-0000FJ-1L; Fri, 28 Feb 2014 18:10:33 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJRt0-0000Bz-QR for linux-arm-kernel@lists.infradead.org; Fri, 28 Feb 2014 18:10:19 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s1SI9U05004865; Fri, 28 Feb 2014 12:09:30 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s1SI9US6030104; Fri, 28 Feb 2014 12:09:30 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Fri, 28 Feb 2014 12:09:29 -0600 Received: from khorivan.synapse.com (incasgf5a_e1_2.itg.ti.com [10.167.216.36]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s1SI8t4r003787; Fri, 28 Feb 2014 12:09:23 -0600 From: Ivan Khoronzhuk To: Subject: [PATCH 4/5] ARM: dts: keystone: update reset node to work with reset driver Date: Fri, 28 Feb 2014 20:07:44 +0200 Message-ID: <1393610865-23630-5-git-send-email-ivan.khoronzhuk@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393610865-23630-1-git-send-email-ivan.khoronzhuk@ti.com> References: <1393610865-23630-1-git-send-email-ivan.khoronzhuk@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140228_131015_030212_47B6389A X-CRM114-Status: UNSURE ( 9.15 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -3.8 (---) Cc: Mark Rutland , linux-doc@vger.kernel.org, catalin.marinas@arm.com, devicetree@vger.kernel.org, ldewangan@nvidia.com, Russell King , anton@enomsg.org, lho@apm.com, abhimany@codeaurora.org, ksankaran@apm.com, fkan@apm.com, grygorii.strashko@ti.com, Pawel Moll , Ian Campbell , w-kwok2@ti.com, Rob Herring , linux-arm-kernel@lists.infradead.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, Kumar Gala , olof@lixom.net, Ivan Khoronzhuk X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The reset controller registers are part of the PLL Controller MMRs. According to TRM there are the following registers: RSTYPE, RSCTRL, RSCFG and RSISO. Currently declared only one of them, but that is not enough to correctly setup reset properties, so add whole range of pll registers - pllregs. Also add range for reset multiplex registers for SoC on the device. These registers are located in Bootcfg memory space and needed to setup behaviour after appropriate watchdog is triggered. Add "ti,wdt_list" option to declare what watchdog are used to reboot the SoC. Signed-off-by: Ivan Khoronzhuk --- CC: Rob Herring CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: Russell King arch/arm/boot/dts/keystone.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 3a83ffe..7092208 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -99,7 +99,9 @@ rstctrl: reset-controller { compatible = "ti,keystone-reset"; - reg = <0x023100e8 4>; /* pll reset control reg */ + reg = <0x23100e4 0x10>, <0x2620328 0x10>; + reg-names = "pllregs", "muxregs"; + ti,wdt_list = <0>; }; /include/ "keystone-clocks.dtsi"