From patchwork Fri Feb 28 20:42:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 3744131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9696F9F2F7 for ; Fri, 28 Feb 2014 20:47:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C244B20259 for ; Fri, 28 Feb 2014 20:47:34 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7FF820260 for ; Fri, 28 Feb 2014 20:47:33 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJUJq-0002Rc-LO; Fri, 28 Feb 2014 20:46:07 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJUJH-0004LU-Dt; Fri, 28 Feb 2014 20:45:31 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WJUIS-00049q-Oy for linux-arm-kernel@lists.infradead.org; Fri, 28 Feb 2014 20:44:43 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s1SKiIO7008041; Fri, 28 Feb 2014 14:44:18 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s1SKiIvr029450; Fri, 28 Feb 2014 14:44:18 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Fri, 28 Feb 2014 14:44:17 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s1SKiHx3003602; Fri, 28 Feb 2014 14:44:17 -0600 Received: from localhost (irmo.am.dhcp.ti.com [128.247.71.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s1SKiHt09315; Fri, 28 Feb 2014 14:44:17 -0600 (CST) From: Suman Anna To: Joerg Roedel , Tony Lindgren Subject: [PATCHv3 06/13] iommu/omap: enable bus-error back on supported iommus Date: Fri, 28 Feb 2014 14:42:37 -0600 Message-ID: <1393620164-14633-7-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1393620164-14633-1-git-send-email-s-anna@ti.com> References: <1393620164-14633-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140228_154440_987019_FD360AD0 X-CRM114-Status: GOOD ( 15.46 ) X-Spam-Score: -6.9 (------) Cc: devicetree@vger.kernel.org, Suman Anna , Subramaniam Chanderashekarapuram , iommu@lists.linux-foundation.org, Laurent Pinchart , Florian Vaussard , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The remoteproc MMUs in OMAP4+ SoCs have some additional debug registers that can give out the PC value in addition to the MMU fault address. The PC value can be extracted properly only on the DSP cores, and is not available on the ARM processors within the IPU sub-systems. Instead, the MMUs have been enhanced to throw a bus-error response back to the IPU processors. This functionality is programmable through the MMU_GP_REG register. The cores are simply stalled if the MMU_GP_REG.BUS_ERR_BACK_EN bit is not set. When set, a bus-error exception is raised allowing the processor to handle it as a bus fault and provide additional debug information. This feature is turned on by default by the driver on iommus supporting it. Signed-off-by: Subramaniam Chanderashekarapuram Signed-off-by: Suman Anna --- drivers/iommu/omap-iommu.c | 2 ++ drivers/iommu/omap-iommu.h | 5 +++++ drivers/iommu/omap-iommu2.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index eb73ef2..28bc631 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -961,6 +961,8 @@ static int omap_iommu_probe(struct platform_device *pdev) */ obj->da_start = 0; obj->da_end = 0xfffff000; + if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) + obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; } else { obj->nr_tlb_entries = pdata->nr_tlb_entries; obj->name = pdata->name; diff --git a/drivers/iommu/omap-iommu.h b/drivers/iommu/omap-iommu.h index 1200842..ea920c3 100644 --- a/drivers/iommu/omap-iommu.h +++ b/drivers/iommu/omap-iommu.h @@ -52,6 +52,8 @@ struct omap_iommu { void *ctx; /* iommu context: registres saved area */ u32 da_start; u32 da_end; + + int has_bus_err_back; }; struct cr_regs { @@ -130,6 +132,7 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) #define MMU_READ_CAM 0x68 #define MMU_READ_RAM 0x6c #define MMU_EMU_FAULT_AD 0x70 +#define MMU_GP_REG 0x88 #define MMU_REG_SIZE 256 @@ -163,6 +166,8 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) #define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK +#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1 + /* * utilities for super page(16MB, 1MB, 64KB and 4KB) */ diff --git a/drivers/iommu/omap-iommu2.c b/drivers/iommu/omap-iommu2.c index d745094..5e1ea3b 100644 --- a/drivers/iommu/omap-iommu2.c +++ b/drivers/iommu/omap-iommu2.c @@ -98,6 +98,9 @@ static int omap2_iommu_enable(struct omap_iommu *obj) iommu_write_reg(obj, pa, MMU_TTB); + if (obj->has_bus_err_back) + iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); + __iommu_set_twl(obj, true); return 0;