From patchwork Mon Mar 3 15:07:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 3755091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 90418BF13A for ; Mon, 3 Mar 2014 15:47:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A128520179 for ; Mon, 3 Mar 2014 15:47:47 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 815AD2015A for ; Mon, 3 Mar 2014 15:47:46 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WKUVb-0003SG-0Q; Mon, 03 Mar 2014 15:10:24 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WKUUk-000236-UF; Mon, 03 Mar 2014 15:09:30 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WKUTl-0001r0-Jl for linux-arm-kernel@lists.infradead.org; Mon, 03 Mar 2014 15:08:31 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s23F8C7j030969; Mon, 3 Mar 2014 09:08:12 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s23F8Chu017183; Mon, 3 Mar 2014 09:08:12 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Mon, 3 Mar 2014 09:08:11 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s23F7Z1D008921; Mon, 3 Mar 2014 09:08:08 -0600 From: Roger Quadros To: , , Subject: [PATCH 09/12] phy: ti-pipe3: streamline PHY operations Date: Mon, 3 Mar 2014 17:07:31 +0200 Message-ID: <1393859254-10937-10-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393859254-10937-1-git-send-email-rogerq@ti.com> References: <1393859254-10937-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140303_100829_828361_7F7B33AD X-CRM114-Status: GOOD ( 15.51 ) X-Spam-Score: -3.9 (---) Cc: devicetree@vger.kernel.org, george.cherian@ti.com, balajitk@ti.com, linux-ide@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, hdegoede@redhat.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Limit .power_on() and .power_off() to just control the PHY power and not the DPLL. The DPLL will be enabled in .init() and idled in .exit(). Don't reprogram the DPLL if it has been already locked by the bootloader. This fixes a problem with SATA, where it fails if SATA was used by the bootloader. Signed-off-by: Roger Quadros --- drivers/phy/phy-ti-pipe3.c | 114 +++++++++++++++++++++++++-------------------- 1 file changed, 63 insertions(+), 51 deletions(-) diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index ee8871d..d3c085a 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -47,7 +47,8 @@ #define PLL_SD_MASK 0x0003FC00 #define PLL_SD_SHIFT 10 #define SET_PLL_GO 0x1 -#define PLL_TICOPWDN 0x10000 +#define PLL_LDOPWDN BIT(15) +#define PLL_TICOPWDN BIT(16) #define PLL_LOCK 0x2 #define PLL_IDLE 0x1 @@ -56,7 +57,8 @@ * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status * to be correctly reflected in the PIPE3PHY_PLL_STATUS register. */ -# define PLL_IDLE_TIME 100; +#define PLL_IDLE_TIME 100 /* in milliseconds */ +#define PLL_LOCK_TIME 100 /* in milliseconds */ struct pipe3_dpll_params { u16 m; @@ -132,24 +134,6 @@ static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) static int ti_pipe3_power_off(struct phy *x) { struct ti_pipe3 *phy = phy_get_drvdata(x); - int val; - int timeout = PLL_IDLE_TIME; - - val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val |= PLL_IDLE; - ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - do { - val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (val & PLL_TICOPWDN) - break; - udelay(5); - } while (--timeout); - - if (!timeout) { - dev_err(phy->dev, "power off failed\n"); - return -EBUSY; - } omap_control_phy_power(phy->control_dev, 0); @@ -159,44 +143,34 @@ static int ti_pipe3_power_off(struct phy *x) static int ti_pipe3_power_on(struct phy *x) { struct ti_pipe3 *phy = phy_get_drvdata(x); - int val; - int timeout = PLL_IDLE_TIME; - - val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_IDLE; - ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - do { - val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (!(val & PLL_TICOPWDN)) - break; - udelay(5); - } while (--timeout); - - if (!timeout) { - dev_err(phy->dev, "power on failed\n"); - return -EBUSY; - } + omap_control_phy_power(phy->control_dev, 1); return 0; } -static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy) +static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) { u32 val; unsigned long timeout; - ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - - timeout = jiffies + msecs_to_jiffies(20); + timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME); do { + cpu_relax(); val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); if (val & PLL_LOCK) break; - } while (!WARN_ON(time_after(jiffies, timeout))); + } while (!time_after(jiffies, timeout)); + + if (!(val & PLL_LOCK)) { + dev_err(phy->dev, "DPLL failed to lock\n"); + return -EBUSY; + } + + return 0; } -static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy) +static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) { u32 val; struct pipe3_dpll_params *dpll_params; @@ -230,27 +204,65 @@ static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy) val |= dpll_params->sd << PLL_SD_SHIFT; ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); - ti_pipe3_dpll_relock(phy); + ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - return 0; + return ti_pipe3_dpll_wait_lock(phy); } static int ti_pipe3_init(struct phy *x) { struct ti_pipe3 *phy = phy_get_drvdata(x); - int ret; + u32 val; + int ret = 0; - ret = ti_pipe3_dpll_lock(phy); - if (ret) - return ret; + /* Bring it out of IDLE if it is IDLE */ + val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + if (val & PLL_IDLE) { + val &= ~PLL_IDLE; + ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + ret = ti_pipe3_dpll_wait_lock(phy); + } - omap_control_phy_power(phy->control_dev, 1); + /* Program the DPLL only if not locked */ + val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (!(val & PLL_LOCK)) + if (ti_pipe3_dpll_program(phy)) + return -EINVAL; - return 0; + return ret; } +static int ti_pipe3_exit(struct phy *x) +{ + struct ti_pipe3 *phy = phy_get_drvdata(x); + u32 val; + unsigned long timeout; + + /* Put DPLL in IDLE mode */ + val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val |= PLL_IDLE; + ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + /* wait for LDO and Oscillator to power down */ + timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); + do { + cpu_relax(); + val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) + break; + } while (!time_after(jiffies, timeout)); + + if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { + dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", + val); + return -EBUSY; + } + + return 0; +} static struct phy_ops ops = { .init = ti_pipe3_init, + .exit = ti_pipe3_exit, .power_on = ti_pipe3_power_on, .power_off = ti_pipe3_power_off, .owner = THIS_MODULE,