From patchwork Mon Oct 5 03:07:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sarbojit Ganguly X-Patchwork-Id: 7324511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 241B5BEEA4 for ; Mon, 5 Oct 2015 03:10:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 52E912061C for ; Mon, 5 Oct 2015 03:10:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 24FC12061B for ; Mon, 5 Oct 2015 03:10:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ziw8W-00061X-AH; Mon, 05 Oct 2015 03:08:24 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ziw8S-0005qT-WA for linux-arm-kernel@lists.infradead.org; Mon, 05 Oct 2015 03:08:21 +0000 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NVQ01BV98P93K90@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Mon, 05 Oct 2015 12:07:57 +0900 (KST) Received: from epcpsbgx2.samsung.com ( [172.20.52.123]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id A1.AA.05385.D89E1165; Mon, 5 Oct 2015 12:07:57 +0900 (KST) X-AuditID: cbfee691-f79d66d000001509-fb-5611e98de7d3 Received: from epmailer03 ( [203.254.219.143]) by epcpsbgx2.samsung.com (EPCPMTA) with SMTP id AB.59.04967.D89E1165; Mon, 5 Oct 2015 12:07:57 +0900 (KST) Date: Mon, 05 Oct 2015 03:07:57 +0000 (GMT) From: Sarbojit Ganguly Subject: [PATCH v2] arm: Adding support for atomic half word exchange To: linux@arm.linux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com MIME-version: 1.0 X-MTR: 20151005030455699@ganguly.s Msgkey: 20151005030455699@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20151005030455699@ganguly.s X-ParentMTR: X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general MIME-version: 1.0 Message-id: <1394429506.566981444014475210.JavaMail.weblogic@epmlwas08c> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGIsWRmVeSWpSXmKPExsWyRsSkWrf3pWCYwfdtkhabHl9jdWD02Lyk PoAxissmJTUnsyy1SN8ugStjxsprrAX7hCouTm1gaWD8I9jFyMEhJKAi0TcpoouRk0NCwETi 36oGVghbTOLCvfVsXYxcQCVLGSUObZ3DAlPUufsNK0RiDqPEwZfPGEESLECDzn89yQxiswno S5ze/5IJxBYWcJVo/LMYbKqIQLREy7dv7CDNzAJXmSSmHv8ANlVIQF6i/cV2sAZeAUGJkzOf QG1Tkph1cCIrRFxZ4s38b1DnyUksmXqZCcLmlZjR/pQFJj7t6xpmCFta4vysDYww7yz+/hgq zi9x7PYOqF4BialnDkLVqEs87tjDDmHzSaxZ+JYFpn7XqeXMMLsaNv6GqpGQ2NryBOweZgFF iSndD9khbAOJI4vmsKL7hVfAQ2LGtLnMIM9LCEzkkHh4ZgrbBEalWUjqZiGZNQvJLGQ1CxhZ VjGKphYkFxQnpReZ6hUn5haX5qXrJefnbmIEJofT/55N3MF4/4D1IUYBDkYlHl6JJMEwIdbE suLK3EOMpsCImsgsJZqcD0xBeSXxhsZmRhamJqbGRuaWZkrivDrSP4OFBNITS1KzU1MLUovi i0pzUosPMTJxcEo1MO4+6Jp41XpeGft+7aPf+W5I5VX8fnPm+GT+HUIbHj64dcDjg26Ntdfe 6W7JFtb2f1t23E3lNVmwn0FLXUrhO3NmSPBkt5n/u/du6hacNtk3qvevauenvTzNU/+vCuV6 +q/TZSvP/Z99fl1qfgd3GjXzblu1UC/SJddZ/bei0LdNKZzMP6QWMiqxFGckGmoxFxUnAgAT GdefCQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsVy+t/tft3el4JhBptbhC02Pb7G6sDosXlJ fQBjVJpNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtBQ JYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUrShuZGekYGeqZGeoWmslaGBgZEpUE1CWsaM lddYC/YJVVyc2sDSwPhHsIuRg0NIQEWib1JEFyMnh4SAiUTn7jesELaYxIV769m6GLmASuYw Shx8+YwRJMECVH/+60lmEJtNQF/i9P6XTCC2sICrROOfxWDNIgLREi3fvrGDNDMLXGWSmHr8 AwtIQkhAXqL9xXawBl4BQYmTM5+wQGxTkph1cCIrRFxZ4s38b1BXyEksmXqZCcLmlZjR/pQF Jj7t6xpmCFta4vysDYwwVy/+/hgqzi9x7PYOqF4BialnDkLVqEs87tjDDmHzSaxZ+JYFpn7X qeXMMLsaNv6GqpGQ2NryBOweZgFFiSndD9khbAOJI4vmsKL7hVfAQ2LGtLnMExhlZyFJzULS PgtJO7KaBYwsqxhFUwuSC4qT0iuM9IoTc4tL89L1kvNzNzGCE9GzRTsY/523PsQowMGoxMMr kSQYJsSaWFZcmXuIUYKDWUmEV/UFUIg3JbGyKrUoP76oNCe1+BCjKTDaJjJLiSbnA5NkXkm8 obGJuamxqYWBobm5mZI47429DGFCAumJJanZqakFqUUwfUwcnFINjA4Tpt44Wlh3NiXEYZZu jt71dI1ZHyckJmzWdnmiMu3NAaGZigblwfEPnpzQZrX8r6B6rDWy2u/HmkXW5/9ty98ilrFe KjGgrVfFdvnh+yvV08KytunKLllhYC+65HGdr+bqOZtsl1ScmjKX3VXTMvyDUumKgw3eigbN L6y1F+ib2t8/bJ51TYmlOCPRUIu5qDgRAMkp2rBaAwAA DLP-Filter: Pass X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151004_200821_208794_A6A59249 X-CRM114-Status: GOOD ( 12.17 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ganguly.s@samsung.com Cc: Waiman.Long@hp.com, peterz@infradead.org, VIKRAM MUPPARTHI , linux-kernel@vger.kernel.org, suneel@samsung.com, "Catalin.Marinas@arm.com" , SHARAN ALLUR , torvalds@linux-foundation.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hello Will, This is my second version of the patch which covers the byte exclusive case as pointed out by you. Please share your opinion on this. v1-->v2 : Extended the guard code to cover the byte exchange case as well following opinion of Will Deacon. Checkpatch has been run and issues were taken care of. Since support for half-word atomic exchange was not there and Qspinlock on ARM requires it, modified __xchg() to add support for that as well. ARMv6 and lower does not support ldrex{b,h} so, added a guard code to prevent build breaks. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 916a274..a53cbeb 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size switch (size) { #if __LINUX_ARM_ARCH__ >= 6 +#if !defined(CONFIG_CPU_V6) case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; + + /* + * Half-word atomic exchange, required + * for Qspinlock support on ARM. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n"