From patchwork Thu Mar 13 09:18:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 3823761 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 85BEE9F1CD for ; Thu, 13 Mar 2014 09:24:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BAD332020A for ; Thu, 13 Mar 2014 09:24:54 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C810220176 for ; Thu, 13 Mar 2014 09:24:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WO1qq-0001pM-AE; Thu, 13 Mar 2014 09:22:58 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WO1ps-0000v3-B6; Thu, 13 Mar 2014 09:21:56 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WO1nl-0000bu-96 for linux-arm-kernel@lists.infradead.org; Thu, 13 Mar 2014 09:19:48 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s2D9JC6L004935; Thu, 13 Mar 2014 04:19:12 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2D9JC9U031479; Thu, 13 Mar 2014 04:19:12 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Thu, 13 Mar 2014 04:19:12 -0500 Received: from dflp32.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2D9Ifhc005531; Thu, 13 Mar 2014 04:19:09 -0500 From: Peter Ujfalusi To: , , , , Subject: [PATCH 07/18] DMA: edma: Use different eventq for cyclic channels Date: Thu, 13 Mar 2014 11:18:29 +0200 Message-ID: <1394702320-21743-8-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1394702320-21743-1-git-send-email-peter.ujfalusi@ti.com> References: <1394702320-21743-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140313_051945_623412_17062A4A X-CRM114-Status: UNSURE ( 9.25 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -6.9 (------) Cc: davinci-linux-open-source@linux.davincidsp.com, joelf@ti.com, nsekhar@ti.com, Liam Girdwood , Jyri Sarha , Tony Lindgren , Mark Brown , mporter@linaro.org, dan.j.williams@intel.com, vinod.koul@intel.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To improve latency with cyclic DMA operation it is preferred to use different eventq/tc than the default which is used by all other drivers (mmc, spi, i2c, etc). When preparing the cyclic dma ask for non default queue for the channel which is going to be used with cyclic mode. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 86d6a3fb0d92..604c7c94c731 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -624,6 +624,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( edesc->pset[i].opt |= TCINTEN; } + /* Use different eventq/tc for cyclic DMA to reduce latency */ + edma_request_non_default_queue(echan->ch_num); + return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); }