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[2/4] ARM: sun7i: fix PLL4 clock and add PLL8

Message ID 1395253173-30437-3-git-send-email-emilio@elopez.com.ar (mailing list archive)
State New, archived
Headers show

Commit Message

Emilio López March 19, 2014, 6:19 p.m. UTC
Allwinner reworked the PLL4 clock in sun7i; so we need to change the
compatible. Additionally, PLL8 is compatible with this new PLL4
implementation, so let's add a node for it as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

Comments

Maxime Ripard April 14, 2014, 9:59 a.m. UTC | #1
On Wed, Mar 19, 2014 at 03:19:31PM -0300, Emilio López wrote:
> Allwinner reworked the PLL4 clock in sun7i; so we need to change the
> compatible. Additionally, PLL8 is compatible with this new PLL4
> implementation, so let's add a node for it as well.
> 
> Signed-off-by: Emilio López <emilio@elopez.com.ar>

Applied to sunxi/fixes-for-3.15.

Thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e766c6a..4e58ee5 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -71,7 +71,7 @@ 
 
 		pll4: clk@01c20018 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-pll1-clk";
+			compatible = "allwinner,sun7i-a20-pll4-clk";
 			reg = <0x01c20018 0x4>;
 			clocks = <&osc24M>;
 			clock-output-names = "pll4";
@@ -93,6 +93,14 @@ 
 			clock-output-names = "pll6_sata", "pll6_other", "pll6";
 		};
 
+		pll8: clk@01c20040 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-pll4-clk";
+			reg = <0x01c20040 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll8";
+		};
+
 		cpu: cpu@01c20054 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-cpu-clk";