| Message ID | 1395256879-8475-3-git-send-email-carlo@caione.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Mar 19, 2014 at 08:21:18PM +0100, Carlo Caione wrote: > This patch adds DTS entries for NMI controller as child of GIC. > > Signed-off-by: Carlo Caione <carlo@caione.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Thanks!
Hi, On 03/19/2014 08:21 PM, Carlo Caione wrote: > This patch adds DTS entries for NMI controller as child of GIC. > > Signed-off-by: Carlo Caione <carlo@caione.org> Note this breaks the kernel on sun6i / A31 since we don't have a pmic driver there yet, and thus the nmi gets constantly fired without anything clearing it. So the sun6i section needs a status = "disabled"; until we actually have pmic support. Regards, Hans > --- > arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++ > arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi > index 5256ad9..eea6033 100644 > --- a/arch/arm/boot/dts/sun6i-a31.dtsi > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi > @@ -190,6 +190,14 @@ > #size-cells = <1>; > ranges; > > + nmi_intc: interrupt-controller@01f00c0c { > + compatible = "allwinner,sun6i-a31-sc-nmi"; > + interrupt-controller; > + #interrupt-cells = <2>; > + reg = <0x01f00c0c 0x38>; > + interrupts = <0 0 4>; > + }; > + > pio: pinctrl@01c20800 { > compatible = "allwinner,sun6i-a31-pinctrl"; > reg = <0x01c20800 0x400>; > diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi > index 6f25cf5..7637f12 100644 > --- a/arch/arm/boot/dts/sun7i-a20.dtsi > +++ b/arch/arm/boot/dts/sun7i-a20.dtsi > @@ -339,6 +339,14 @@ > #size-cells = <1>; > ranges; > > + nmi_intc: interrupt-controller@01c00030 { > + compatible = "allwinner,sun7i-a20-sc-nmi"; > + interrupt-controller; > + #interrupt-cells = <2>; > + reg = <0x01c00030 0x0c>; > + interrupts = <0 0 4>; > + }; > + > emac: ethernet@01c0b000 { > compatible = "allwinner,sun4i-a10-emac"; > reg = <0x01c0b000 0x1000>; >
On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote: > Hi, > > On 03/19/2014 08:21 PM, Carlo Caione wrote: > > This patch adds DTS entries for NMI controller as child of GIC. > > > > Signed-off-by: Carlo Caione <carlo@caione.org> > > Note this breaks the kernel on sun6i / A31 since we don't have a > pmic driver there yet, and thus the nmi gets constantly fired without > anything clearing it. > > So the sun6i section needs a status = "disabled"; until we actually have pmic > support. I guess it also applies to the A20, since the PMIC patches will probably get merged later on?
Hi, On 03/26/2014 10:39 AM, Maxime Ripard wrote: > On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote: >> Hi, >> >> On 03/19/2014 08:21 PM, Carlo Caione wrote: >>> This patch adds DTS entries for NMI controller as child of GIC. >>> >>> Signed-off-by: Carlo Caione <carlo@caione.org> >> >> Note this breaks the kernel on sun6i / A31 since we don't have a >> pmic driver there yet, and thus the nmi gets constantly fired without >> anything clearing it. >> >> So the sun6i section needs a status = "disabled"; until we actually have pmic >> support. > > I guess it also applies to the A20, since the PMIC patches will > probably get merged later on? Could be I've never tried it on the A20 without also having the pmic driver build into the kernel. Thinking more about this, I think this actually is a bug in the nmi irqchip driver, it should not unmask the gic irq until it gets an unmask for its child irq itself. Otherwise we can still get the same problem if ie the pmic driver is a module, etc. Hmm, looking at the code I see that it already masks (sets enable to 0) the irq in sunxi_sc_nmi_irq_init. Note that this really should be done before the irq_set_chained_handler call though, as from then on the gic irq is unmasked, so we may get spurious irqs until the sunxi_sc_nmi_write calls are done. I don't think this will solve the A31 problem though, I wonder if the enable reg-offset we've for the A31 is correct, maybe it should be 8 like with the A20 ? I'll give this a try when I can find some time for this. Regards, Hans
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5256ad9..eea6033 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -190,6 +190,14 @@ #size-cells = <1>; ranges; + nmi_intc: interrupt-controller@01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupts = <0 0 4>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 6f25cf5..7637f12 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -339,6 +339,14 @@ #size-cells = <1>; ranges; + nmi_intc: interrupt-controller@01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = <0 0 4>; + }; + emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>;
This patch adds DTS entries for NMI controller as child of GIC. Signed-off-by: Carlo Caione <carlo@caione.org> --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+)