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[88.188.80.5]) by mx.google.com with ESMTPSA id mw3sm9217422wic.7.2014.03.28.10.59.41 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Mar 2014 10:59:44 -0700 (PDT) From: Boris BREZILLON To: Rob Landley , Nicolas Ferre , Jean-Christophe Plagniol-Villard , Thomas Gleixner Subject: [RFC PATCH v2 10/10] ARM: at91/dt: add new AIC irq mux definitions for sama5 SoCs Date: Fri, 28 Mar 2014 18:59:08 +0100 Message-Id: <1396029548-10928-11-git-send-email-b.brezillon.dev@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396029548-10928-1-git-send-email-b.brezillon.dev@gmail.com> References: <1396029548-10928-1-git-send-email-b.brezillon.dev@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140328_140006_357330_11DB7BEE X-CRM114-Status: UNSURE ( 9.26 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.0 (--) Cc: devicetree@vger.kernel.org, Boris BREZILLON , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add irq line muxing definition for sama5 SoCs. Signed-off-by: Boris BREZILLON --- arch/arm/boot/dts/sama5d3.dtsi | 37 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/sama5d3_tcb1.dtsi | 20 +++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 3d5faf8..ece1f7b 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -416,6 +416,43 @@ interrupt-controller; reg = <0xfffff000 0x200>; atmel,external-irqs = <47>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0x0 0xffffc000 0x4000>, + <26 0x0 0xf0010000 0x4000>, + <27 0x0 0xf8014000 0x4000>; + + atmel,aic-irq-mapping = <0xffffffff 0x7ffff>; + + pmc_irq: irq-mux@1,3c64 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <1 0x3c64 0x4>; + atmel,aic-mux-reg-mask = <0x5074b>; + }; + + rtc_irq: irq-mux@1,3ed4 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <1 0x3ed4 0x4>; + atmel,aic-mux-reg-mask = <0x1f>; + }; + + tc0_irq: irq-mux@26,28 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <26 0x28 0x4>; + atmel,aic-mux-reg-mask = <0xff>; + }; + + tc1_irq: irq-mux@26,68 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <26 0x68 0x4>; + atmel,aic-mux-reg-mask = <0xff>; + }; + + tc2_irq: irq-mux@26,a8 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <26 0xa8 0x4>; + atmel,aic-mux-reg-mask = <0xff>; + }; }; pinctrl@fffff200 { diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 382b044..6060bfd 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -18,6 +18,26 @@ ahb { apb { + aic: interrupt-controller@fffff000 { + tc3_irq: irq-mux@27,28 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <27 0x28 0x4>; + atmel,aic-mux-reg-mask = <0xff>; + }; + + tc4_irq: irq-mux@27,68 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <27 0x68 0x4>; + atmel,aic-mux-reg-mask = <0xff>; + }; + + tc5_irq: irq-mux@27,a8 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <27 0xa8 0x4>; + atmel,aic-mux-reg-mask = <0xff>; + }; + }; + pmc: pmc@fffffc00 { periphck { tcb1_clk: tcb1_clk {