From patchwork Fri Mar 28 21:13:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 3907501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 438FE9F334 for ; Fri, 28 Mar 2014 21:16:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4258720274 for ; Fri, 28 Mar 2014 21:16:25 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C65F200DF for ; Fri, 28 Mar 2014 21:16:24 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WTe6k-0007HU-66; Fri, 28 Mar 2014 21:14:35 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WTe6H-0004Ss-Jy; Fri, 28 Mar 2014 21:14:05 +0000 Received: from mail-ie0-f177.google.com ([209.85.223.177]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WTe5S-0004MH-4D for linux-arm-kernel@lists.infradead.org; Fri, 28 Mar 2014 21:13:16 +0000 Received: by mail-ie0-f177.google.com with SMTP id rl12so5486643iec.36 for ; Fri, 28 Mar 2014 14:12:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=14rvWGPCKgxyeOO9DLdEBa2PHkwJb0srvhGpr/oaD6g=; b=dqfkb32k0ALr8IwDXZaug8jfo4g83xdA5kx1tj0RIQgQokCPDEDUrxRNIKltnvOj26 elhTgLro0EEiNuNdRIQtaPmKneGOf1Cps5AbdFCztRWh/53IGtIO53xX1CHDsmd4UOY9 Ucxq7S1MDoeBfysNwnrTWrYWm36PU5Q3KgUHWB1g4kGcC3IS7E1vzXvu8PgX6noTm2qA vptEwDESzYVvCtMo2nevbobswdntpM7XPbuw3pAkRgE74/tl37QKS4/OA0yWsHe9Mz87 vIFxNiwN336f+lpdPl/r0EYwAhdXcnwnx9ksBL/1g+SDTrWNGBIyAxVFiSBVjfMbZbJR 7V2Q== X-Gm-Message-State: ALoCoQkztGjfwjTaEFMqw9YNpvwPpiuIAhTfjgn6Szn8uvCOJ8VgKVVqgsZdy0txYJxZ8s1DHTo/ X-Received: by 10.50.35.129 with SMTP id h1mr13637508igj.17.1396041171136; Fri, 28 Mar 2014 14:12:51 -0700 (PDT) Received: from localhost.localdomain (c-71-195-31-37.hsd1.mn.comcast.net. [71.195.31.37]) by mx.google.com with ESMTPSA id t1sm7139024igw.16.2014.03.28.14.12.50 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Mar 2014 14:12:50 -0700 (PDT) From: Alex Elder To: linux@arm.linux.org.uk, linus.walleij@linaro.org, viresh.linux@gmail.com, shiraz.hashim@gmail.com, catalin.marinas@arm.com Subject: [RFC PATCH 7/7] ARM: spear: use central SMP spin-table routines Date: Fri, 28 Mar 2014 16:13:00 -0500 Message-Id: <1396041180-29897-8-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396041180-29897-1-git-send-email-elder@linaro.org> References: <1396041180-29897-1-git-send-email-elder@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140328_171314_337213_27ADB753 X-CRM114-Status: GOOD ( 27.10 ) X-Spam-Score: -2.6 (--) Cc: devicetree@vger.kernel.org, spear-devel@list.st.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get rid of the spear-specific code that implements the "holding pen" for secondary CPUs. Use the code defined in "arch/arm/kernel/smp.c" instead. Note: The original "holding pen" code for this machine used only the bottom 4 bits of the MPIDR to identify the processor id. The common code looks at the bottom 24 bits. The validity of this change needs to be verified. Signed-off-by: Alex Elder --- arch/arm/mach-spear/Makefile | 2 +- arch/arm/mach-spear/generic.h | 1 - arch/arm/mach-spear/headsmp.S | 47 -------------------------- arch/arm/mach-spear/platsmp.c | 75 ++--------------------------------------- 4 files changed, 4 insertions(+), 121 deletions(-) delete mode 100644 arch/arm/mach-spear/headsmp.S diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile index a946c19..974a417 100644 --- a/arch/arm/mach-spear/Makefile +++ b/arch/arm/mach-spear/Makefile @@ -7,7 +7,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include # Common support obj-y := restart.o time.o -smp-$(CONFIG_SMP) += headsmp.o platsmp.o +smp-$(CONFIG_SMP) += platsmp.o smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o $(smp-y) diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h index a99d90a..86189ec 100644 --- a/arch/arm/mach-spear/generic.h +++ b/arch/arm/mach-spear/generic.h @@ -36,7 +36,6 @@ void __init spear13xx_l2x0_init(void); void spear_restart(enum reboot_mode, const char *); -void spear13xx_secondary_startup(void); void spear13xx_cpu_die(unsigned int cpu); extern struct smp_operations spear13xx_smp_ops; diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S deleted file mode 100644 index ed85473..0000000 --- a/arch/arm/mach-spear/headsmp.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-spear13XX/headsmp.S - * - * Picked from realview - * Copyright (c) 2012 ST Microelectronics Limited - * Shiraz Hashim - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - - __INIT - -/* - * spear13xx specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(spear13xx_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* re-enable coherency */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #(1 << 6) | (1 << 0) - mcr p15, 0, r0, c1, c0, 1 - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - - .align -1: .long . - .long pen_release -ENDPROC(spear13xx_secondary_startup) diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c index e16f779..e97af7d 100644 --- a/arch/arm/mach-spear/platsmp.c +++ b/arch/arm/mach-spear/platsmp.c @@ -20,77 +20,8 @@ #include #include "generic.h" -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - sync_cache_w(&pen_release); -} - -static DEFINE_SPINLOCK(boot_lock); - static void __iomem *scu_base = IOMEM(VA_SCU_BASE); -static void spear13xx_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - write_pen_release(cpu); - - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. @@ -119,14 +50,14 @@ static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus) * (presently it is in SRAM). The BootMonitor waits until it receives a * soft interrupt, and then the secondary CPU branches to this address. */ - __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); + __raw_writel(virt_to_phys(secondary_holding_pen), SYS_LOCATION); } struct smp_operations spear13xx_smp_ops __initdata = { .smp_init_cpus = spear13xx_smp_init_cpus, .smp_prepare_cpus = spear13xx_smp_prepare_cpus, - .smp_secondary_init = spear13xx_secondary_init, - .smp_boot_secondary = spear13xx_boot_secondary, + .smp_secondary_init = smp_secondary_init, + .smp_boot_secondary = smp_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = spear13xx_cpu_die, #endif