From patchwork Mon Mar 31 20:34:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Garg X-Patchwork-Id: 3917701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 04975BF540 for ; Mon, 31 Mar 2014 20:35:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E495203AD for ; Mon, 31 Mar 2014 20:35:22 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56D8A20386 for ; Mon, 31 Mar 2014 20:35:20 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUivC-0005oq-T0; Mon, 31 Mar 2014 20:35:07 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUivA-0006sd-FD; Mon, 31 Mar 2014 20:35:04 +0000 Received: from tx2ehsobe004.messaging.microsoft.com ([65.55.88.14] helo=tx2outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUiv8-0006rx-O4 for linux-arm-kernel@lists.infradead.org; Mon, 31 Mar 2014 20:35:03 +0000 Received: from mail68-tx2-R.bigfish.com (10.9.14.243) by TX2EHSOBE010.bigfish.com (10.9.40.30) with Microsoft SMTP Server id 14.1.225.22; Mon, 31 Mar 2014 20:34:41 +0000 Received: from mail68-tx2 (localhost [127.0.0.1]) by mail68-tx2-R.bigfish.com (Postfix) with ESMTP id 3985D4A0364; Mon, 31 Mar 2014 20:34:41 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zze0eahzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh25cch25f6h2605h268bh1155h) Received: from mail68-tx2 (localhost.localdomain [127.0.0.1]) by mail68-tx2 (MessageSwitch) id 1396298079510704_496; Mon, 31 Mar 2014 20:34:39 +0000 (UTC) Received: from TX2EHSMHS035.bigfish.com (unknown [10.9.14.248]) by mail68-tx2.bigfish.com (Postfix) with ESMTP id 6A0A2140054; Mon, 31 Mar 2014 20:34:39 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS035.bigfish.com (10.9.99.135) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 31 Mar 2014 20:34:38 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 31 Mar 2014 20:34:37 +0000 Received: from b37173-desktop.am.freescale.net (b37173-desktop.am.freescale.net [10.81.16.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s2VKYWZr025971; Mon, 31 Mar 2014 13:34:37 -0700 From: Nitin Garg To: Subject: [PATCH] ARM: errata: workaround Cortex-A9 errata 761320 and 794072 Date: Mon, 31 Mar 2014 15:34:32 -0500 Message-ID: <1396298072-13254-2-git-send-email-nitin.garg@freescale.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1396298072-13254-1-git-send-email-nitin.garg@freescale.com> References: <1396298072-13254-1-git-send-email-nitin.garg@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140331_163502_898384_6EC3C654 X-CRM114-Status: GOOD ( 10.53 ) X-Spam-Score: -4.2 (----) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add workaround for Cortex-A9 errata 761320 ([present on r0, r1, r2, r3) and 794072 (present on all revisions). These are Category B, present on SMP systems. Signed-off-by: Nitin Garg --- arch/arm/Kconfig | 23 +++++++++++++++++++++++ arch/arm/mach-imx/Kconfig | 2 ++ arch/arm/mm/proc-v7.S | 11 +++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a48712e..f8464ff 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1301,6 +1301,29 @@ config ARM_ERRATA_751472 operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. +config ARM_ERRATA_794072 + bool "ARM errata: A short loop including a DMB instruction might cause a denial of service" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 794072 Cortex-A9 + (all revisions). A processor which continuously executes a short + loop containing a DMB instruction might prevent a CP15 operation + broadcast by another processor making further progress, causing + a denial of service. This erratum can be worked around by setting + bit[4] of the undocumented Diagnostic Control Register to 1. + +config ARM_ERRATA_761320 + bool "Full cache line writes to the same memory region from at least two processors might deadlock processor" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 761320 Cortex-A9 (r0..r3). + Under very rare circumstances, full cache line writes + from (at least) 2 processors on cache lines in hazard with + other requests may cause arbitration issues in the SCU, + leading to processor deadlock. This erratum can be + worked around by setting bit[21] of the undocumented + Diagnostic Control Register to 1. + config PL310_ERRATA_753970 bool "PL310 errata: cache sync operation may be faulty" depends on CACHE_PL310 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5740296d..19690c2 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -794,6 +794,8 @@ config SOC_IMX6 config SOC_IMX6Q bool "i.MX6 Quad/DualLite support" select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_794072 if SMP + select ARM_ERRATA_761320 if SMP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select MIGHT_HAVE_PCI diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 195731d..b5e5386 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -337,6 +337,17 @@ __v7_setup: mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 1: #endif +#ifdef CONFIG_ARM_ERRATA_794072 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 4 @ set bit #4 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_761320 + cmp r6, #0x40 @ present prior to r4p0 + mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrlt r10, r10, #1 << 21 @ set bit #21 + mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif /* Cortex-A15 Errata */ 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number