From patchwork Tue Apr 1 08:03:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 3919281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3E6BF9F2B6 for ; Tue, 1 Apr 2014 08:07:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2D2E5203AF for ; Tue, 1 Apr 2014 08:07:26 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 008EA20380 for ; Tue, 1 Apr 2014 08:07:25 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUthL-0000zX-0V; Tue, 01 Apr 2014 08:05:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUth1-00028J-0s; Tue, 01 Apr 2014 08:05:11 +0000 Received: from mail-pb0-f43.google.com ([209.85.160.43]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUtgw-00025g-UB for linux-arm-kernel@lists.infradead.org; Tue, 01 Apr 2014 08:05:08 +0000 Received: by mail-pb0-f43.google.com with SMTP id um1so9457143pbc.16 for ; Tue, 01 Apr 2014 01:04:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VUH5h8fVuJkG2k5oHQFXos66qlu5urL16+LLI0Krav4=; b=lmvIXb11CUr8c0t6AK5I9m1colM63+OsyISCigumg/8K0iM3VA7NcmgnZT8SI8REcq b6SFhn8UyZR6pFYd2VbhiNcVw5fYwaGJWC5TLkvZH2qBkPBQI6UaZI/PCnLQxbaQviyA 1G1pVcXj3qGM0mwiAr77JVaSFxk5UUNNOmYvRfvxwQlYYyDQc6pS4eNUIkEi3ox+4Imm o00OhOmDxKx+puDjglytXrXo4651beg9R3lpsFTqHsANtqHMzHF2Mem+QQDgb2i68Wgw IMzjHeGHULLtbsm0OJhBcfUXysPsGEGaG3ytZF4JYlywaCpkHY1iCWcbGgM2a5l9U/VD jebg== X-Gm-Message-State: ALoCoQkfYS7+w1aoCylTG/QmKdRAUBKGYkeTpO8Xyg4DLR5zbv2RkYWyHLbK3x1vpIbfPjOJUqsg X-Received: by 10.66.137.109 with SMTP id qh13mr29787086pab.39.1396339485378; Tue, 01 Apr 2014 01:04:45 -0700 (PDT) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id yo9sm52327508pab.16.2014.04.01.01.04.37 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Apr 2014 01:04:44 -0700 (PDT) From: Haojian Zhuang To: tglx@linutronix.de, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, olof@lixom.net, khilman@kernel.org, xuwei5@hisilicon.com Subject: [PATCH v1 4/8] irq: gic: extends the cpu interface to 16 Date: Tue, 1 Apr 2014 16:03:46 +0800 Message-Id: <1396339430-21084-5-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396339430-21084-1-git-send-email-haojian.zhuang@linaro.org> References: <1396339430-21084-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140401_040507_153305_541C9F2A X-CRM114-Status: GOOD ( 17.56 ) X-Spam-Score: -2.6 (--) Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support 16 CPUs, Hisilicon extends the GIC to support the number of CPU interfaces from 8 to 16. Signed-off-by: Haojian Zhuang --- drivers/irqchip/irq-gic.c | 78 ++++++++++++++++++++++++++++------------------- 1 file changed, 47 insertions(+), 31 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 8fd27bf..44eff46 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -76,9 +76,12 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock); * The GIC mapping of CPU interfaces does not necessarily match * the logical CPU numbering. Let's use a mapping as returned * by the GIC itself. + * + * Hisilicon HiP04 extends the number of CPU interface from 8 to 16. */ -#define NR_GIC_CPU_IF 8 -static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; +#define MAX_NR_GIC_CPU_IF 16 +static u16 gic_cpu_map[MAX_NR_GIC_CPU_IF] __read_mostly; +static int nr_gic_cpu_if = 8; /* The standard GIC supports 8 CPUs */ /* * Supported arch specific GIC irq extension. @@ -245,16 +248,19 @@ static int gic_retrigger(struct irq_data *d) static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { - void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); - unsigned int shift = (gic_irq(d) % 4) * 8; + void __iomem *reg; + unsigned int shift, step; unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); u32 val, mask, bit; - - if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) + if (cpu >= nr_gic_cpu_if || cpu >= nr_cpu_ids) return -EINVAL; + step = BITS_PER_LONG / nr_gic_cpu_if; + shift = (gic_irq(d) % step) * nr_gic_cpu_if; + reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) / step * 4); + raw_spin_lock(&irq_controller_lock); - mask = 0xff << shift; + mask = ((1 << nr_gic_cpu_if) - 1) << shift; bit = gic_cpu_map[cpu] << shift; val = readl_relaxed(reg) & ~mask; writel_relaxed(val | bit, reg); @@ -354,15 +360,17 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) irq_set_chained_handler(irq, gic_handle_cascade_irq); } -static u8 gic_get_cpumask(struct gic_chip_data *gic) +static u16 gic_get_cpumask(struct gic_chip_data *gic) { void __iomem *base = gic_data_dist_base(gic); - u32 mask, i; - - for (i = mask = 0; i < 32; i += 4) { - mask = readl_relaxed(base + GIC_DIST_TARGET + i); - mask |= mask >> 16; - mask |= mask >> 8; + u32 mask, i, j, step; + + /* get the number of CPU fields in GIC_DIST_TARGET register */ + step = BITS_PER_LONG / nr_gic_cpu_if; + for (i = mask = 0; i < 32; i += step) { + mask = readl_relaxed(base + GIC_DIST_TARGET + i / step * 4); + for (j = BITS_PER_LONG >> 1; j >= nr_gic_cpu_if; j >>= 1) + mask |= mask >> j; if (mask) break; } @@ -375,7 +383,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic) static void __init gic_dist_init(struct gic_chip_data *gic) { - unsigned int i; + unsigned int i, step; u32 cpumask; unsigned int gic_irqs = gic->gic_irqs; void __iomem *base = gic_data_dist_base(gic); @@ -392,10 +400,11 @@ static void __init gic_dist_init(struct gic_chip_data *gic) * Set all global interrupts to this CPU only. */ cpumask = gic_get_cpumask(gic); - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - for (i = 32; i < gic_irqs; i += 4) - writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); + for (i = nr_gic_cpu_if; i < BITS_PER_LONG; i <<= 1) + cpumask |= cpumask << i; + step = BITS_PER_LONG / nr_gic_cpu_if; + for (i = 32; i < gic_irqs; i += step) + writel_relaxed(cpumask, base + GIC_DIST_TARGET + i / step * 4); /* * Set priority on all global interrupts. @@ -423,7 +432,7 @@ static void gic_cpu_init(struct gic_chip_data *gic) /* * Get what the GIC says our CPU mask is. */ - BUG_ON(cpu >= NR_GIC_CPU_IF); + BUG_ON(cpu >= nr_gic_cpu_if); cpu_mask = gic_get_cpumask(gic); gic_cpu_map[cpu] = cpu_mask; @@ -431,7 +440,7 @@ static void gic_cpu_init(struct gic_chip_data *gic) * Clear our mask from the other map entries in case they're * still undefined. */ - for (i = 0; i < NR_GIC_CPU_IF; i++) + for (i = 0; i < nr_gic_cpu_if; i++) if (i != cpu) gic_cpu_map[i] &= ~cpu_mask; @@ -469,7 +478,7 @@ static void gic_dist_save(unsigned int gic_nr) { unsigned int gic_irqs; void __iomem *dist_base; - int i; + int i, step; if (gic_nr >= MAX_GIC_NR) BUG(); @@ -484,7 +493,8 @@ static void gic_dist_save(unsigned int gic_nr) gic_data[gic_nr].saved_spi_conf[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) + step = BITS_PER_LONG / nr_gic_cpu_if; + for (i = 0; i < DIV_ROUND_UP(gic_irqs, step); i++) gic_data[gic_nr].saved_spi_target[i] = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); @@ -503,7 +513,7 @@ static void gic_dist_save(unsigned int gic_nr) static void gic_dist_restore(unsigned int gic_nr) { unsigned int gic_irqs; - unsigned int i; + unsigned int i, step; void __iomem *dist_base; if (gic_nr >= MAX_GIC_NR) @@ -525,7 +535,8 @@ static void gic_dist_restore(unsigned int gic_nr) writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) + step = BITS_PER_LONG / nr_gic_cpu_if; + for (i = 0; i < DIV_ROUND_UP(gic_irqs, step); i++) writel_relaxed(gic_data[gic_nr].saved_spi_target[i], dist_base + GIC_DIST_TARGET + i * 4); @@ -666,8 +677,8 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) dmb(ishst); /* this always happens on GIC0 */ - writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - + writel_relaxed(map << (8 + 16 - nr_gic_cpu_if) | irq, + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); raw_spin_unlock_irqrestore(&irq_controller_lock, flags); } #endif @@ -681,7 +692,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) */ void gic_send_sgi(unsigned int cpu_id, unsigned int irq) { - BUG_ON(cpu_id >= NR_GIC_CPU_IF); + BUG_ON(cpu_id >= nr_gic_cpu_if); cpu_id = 1 << cpu_id; /* this always happens on GIC0 */ writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); @@ -700,7 +711,7 @@ int gic_get_cpu_id(unsigned int cpu) { unsigned int cpu_bit; - if (cpu >= NR_GIC_CPU_IF) + if (cpu >= nr_gic_cpu_if) return -1; cpu_bit = gic_cpu_map[cpu]; if (cpu_bit & (cpu_bit - 1)) @@ -971,8 +982,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, * Initialize the CPU interface map to all CPUs. * It will be refined as each CPU probes its ID. */ - for (i = 0; i < NR_GIC_CPU_IF; i++) - gic_cpu_map[i] = 0xff; + for (i = 0; i < nr_gic_cpu_if; i++) + gic_cpu_map[i] = (1 << MAX_NR_GIC_CPU_IF) - 1; /* * For primary GICs, skip over SGIs. @@ -1047,6 +1058,10 @@ gic_of_init(struct device_node *node, struct device_node *parent) if (WARN_ON(!node)) return -ENODEV; + /* HiP04 supports 16 CPUs at most */ + if (of_device_is_compatible(node, "hisilicon,hip04-gic")) + nr_gic_cpu_if = 16; + dist_base = of_iomap(node, 0); WARN(!dist_base, "unable to map gic dist registers\n"); @@ -1069,6 +1084,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); +IRQCHIP_DECLARE(hip04_gic, "hisilicon,hip04-gic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);