From patchwork Wed Apr 9 13:51:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 3955651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3DC479F371 for ; Wed, 9 Apr 2014 13:56:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6D54E20520 for ; Wed, 9 Apr 2014 13:56:25 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 76371200D4 for ; Wed, 9 Apr 2014 13:56:24 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXswe-0002pJ-Oe; Wed, 09 Apr 2014 13:53:42 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXswA-0002rD-Gj; Wed, 09 Apr 2014 13:53:10 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXsvN-0002hj-Ce for linux-arm-kernel@lists.infradead.org; Wed, 09 Apr 2014 13:52:23 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id AF56B9CD; Wed, 9 Apr 2014 15:51:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1B9AD7FC; Wed, 9 Apr 2014 15:51:39 +0200 (CEST) From: Boris BREZILLON To: Randy Dunlap , Maxime Ripard , =?UTF-8?q?Emilio=20L=C3=B3pez?= , Mike Turquette , Linus Walleij Subject: [PATCH 15/15] ARM: sunxi: dt: add support for A31's PL pins Date: Wed, 9 Apr 2014 15:51:18 +0200 Message-Id: <1397051478-4113-16-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1397051478-4113-1-git-send-email-boris.brezillon@free-electrons.com> References: <1397051478-4113-1-git-send-email-boris.brezillon@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140409_095221_651176_1E1B68DA X-CRM114-Status: UNSURE ( 8.95 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.5 (-) Cc: devicetree@vger.kernel.org, Boris BREZILLON , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The A31 SoC control its PL pins using a different memory, and needs both a new gate clk and a reset line to enable these PL port. Signed-off-by: Boris BREZILLON --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index ed9c2c1..90b3a25 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -210,13 +210,17 @@ pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; - reg = <0x01c20800 0x400>; + reg = <0x01c20800 0x400>, + <0x01f02c00 0x400>; interrupts = <0 11 4>, <0 15 4>, <0 16 4>, <0 17 4>; - clocks = <&apb1_gates 5>; - clock-names = "pio_clk"; + clocks = <&apb1_gates 5>, + <&apb0_gates 0>; + clock-names = "pio_clk", "pioL_clk"; + resets = <&apb0_rst 0>; + gpio-controller; interrupt-controller; #address-cells = <1>;