From patchwork Thu Apr 10 13:52:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 3964821 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BEE679F336 for ; Thu, 10 Apr 2014 20:47:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D880D20826 for ; Thu, 10 Apr 2014 20:47:20 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C82442082E for ; Thu, 10 Apr 2014 20:47:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYJsB-0005jX-5D; Thu, 10 Apr 2014 18:38:52 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYJrM-0002aq-AA; Thu, 10 Apr 2014 18:38:00 +0000 Received: from bombadil.infradead.org ([2001:1868:205::9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYJlh-0001wz-3P for linux-arm-kernel@merlin.infradead.org; Thu, 10 Apr 2014 18:32:09 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYFQs-0006OC-E9 for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2014 13:54:23 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 5EB9F839; Thu, 10 Apr 2014 15:53:57 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 6C0C4912; Thu, 10 Apr 2014 15:53:56 +0200 (CEST) From: Boris BREZILLON To: Randy Dunlap , Maxime Ripard , =?UTF-8?q?Emilio=20L=C3=B3pez?= , Mike Turquette , Linus Walleij , Chen-Yu Tsai , Hans de Goede Subject: [PATCH v3 3/7] pinctrl: sunxi: add PL and PM pin definitions Date: Thu, 10 Apr 2014 15:52:42 +0200 Message-Id: <1397137966-30818-4-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1397137966-30818-1-git-send-email-boris.brezillon@free-electrons.com> References: <1397137966-30818-1-git-send-email-boris.brezillon@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140410_065422_908044_A170657E X-CRM114-Status: UNSURE ( 8.42 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.2 (+) Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, dev@linux-sunxi.org, Boris BREZILLON , linux-kernel@vger.kernel.org, Shuge , kevin@allwinnertech.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Define PL and PM pin macros. Signed-off-by: Boris BREZILLON Acked-by: Maxime Ripard --- drivers/pinctrl/pinctrl-sunxi.h | 68 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h index 552b0e9..ed3c4d7 100644 --- a/drivers/pinctrl/pinctrl-sunxi.h +++ b/drivers/pinctrl/pinctrl-sunxi.h @@ -25,6 +25,8 @@ #define PG_BASE 192 #define PH_BASE 224 #define PI_BASE 256 +#define PL_BASE 352 +#define PM_BASE 384 #define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0") #define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1") @@ -323,6 +325,72 @@ #define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30") #define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31") +#define SUNXI_PINCTRL_PIN_PL0 PINCTRL_PIN(PL_BASE + 0, "PL0") +#define SUNXI_PINCTRL_PIN_PL1 PINCTRL_PIN(PL_BASE + 1, "PL1") +#define SUNXI_PINCTRL_PIN_PL2 PINCTRL_PIN(PL_BASE + 2, "PL2") +#define SUNXI_PINCTRL_PIN_PL3 PINCTRL_PIN(PL_BASE + 3, "PL3") +#define SUNXI_PINCTRL_PIN_PL4 PINCTRL_PIN(PL_BASE + 4, "PL4") +#define SUNXI_PINCTRL_PIN_PL5 PINCTRL_PIN(PL_BASE + 5, "PL5") +#define SUNXI_PINCTRL_PIN_PL6 PINCTRL_PIN(PL_BASE + 6, "PL6") +#define SUNXI_PINCTRL_PIN_PL7 PINCTRL_PIN(PL_BASE + 7, "PL7") +#define SUNXI_PINCTRL_PIN_PL8 PINCTRL_PIN(PL_BASE + 8, "PL8") +#define SUNXI_PINCTRL_PIN_PL9 PINCTRL_PIN(PL_BASE + 9, "PL9") +#define SUNXI_PINCTRL_PIN_PL10 PINCTRL_PIN(PL_BASE + 10, "PL10") +#define SUNXI_PINCTRL_PIN_PL11 PINCTRL_PIN(PL_BASE + 11, "PL11") +#define SUNXI_PINCTRL_PIN_PL12 PINCTRL_PIN(PL_BASE + 12, "PL12") +#define SUNXI_PINCTRL_PIN_PL13 PINCTRL_PIN(PL_BASE + 13, "PL13") +#define SUNXI_PINCTRL_PIN_PL14 PINCTRL_PIN(PL_BASE + 14, "PL14") +#define SUNXI_PINCTRL_PIN_PL15 PINCTRL_PIN(PL_BASE + 15, "PL15") +#define SUNXI_PINCTRL_PIN_PL16 PINCTRL_PIN(PL_BASE + 16, "PL16") +#define SUNXI_PINCTRL_PIN_PL17 PINCTRL_PIN(PL_BASE + 17, "PL17") +#define SUNXI_PINCTRL_PIN_PL18 PINCTRL_PIN(PL_BASE + 18, "PL18") +#define SUNXI_PINCTRL_PIN_PL19 PINCTRL_PIN(PL_BASE + 19, "PL19") +#define SUNXI_PINCTRL_PIN_PL20 PINCTRL_PIN(PL_BASE + 20, "PL20") +#define SUNXI_PINCTRL_PIN_PL21 PINCTRL_PIN(PL_BASE + 21, "PL21") +#define SUNXI_PINCTRL_PIN_PL22 PINCTRL_PIN(PL_BASE + 22, "PL22") +#define SUNXI_PINCTRL_PIN_PL23 PINCTRL_PIN(PL_BASE + 23, "PL23") +#define SUNXI_PINCTRL_PIN_PL24 PINCTRL_PIN(PL_BASE + 24, "PL24") +#define SUNXI_PINCTRL_PIN_PL25 PINCTRL_PIN(PL_BASE + 25, "PL25") +#define SUNXI_PINCTRL_PIN_PL26 PINCTRL_PIN(PL_BASE + 26, "PL26") +#define SUNXI_PINCTRL_PIN_PL27 PINCTRL_PIN(PL_BASE + 27, "PL27") +#define SUNXI_PINCTRL_PIN_PL28 PINCTRL_PIN(PL_BASE + 28, "PL28") +#define SUNXI_PINCTRL_PIN_PL29 PINCTRL_PIN(PL_BASE + 29, "PL29") +#define SUNXI_PINCTRL_PIN_PL30 PINCTRL_PIN(PL_BASE + 30, "PL30") +#define SUNXI_PINCTRL_PIN_PL31 PINCTRL_PIN(PL_BASE + 31, "PL31") + +#define SUNXI_PINCTRL_PIN_PM0 PINCTRL_PIN(PM_BASE + 0, "PM0") +#define SUNXI_PINCTRL_PIN_PM1 PINCTRL_PIN(PM_BASE + 1, "PM1") +#define SUNXI_PINCTRL_PIN_PM2 PINCTRL_PIN(PM_BASE + 2, "PM2") +#define SUNXI_PINCTRL_PIN_PM3 PINCTRL_PIN(PM_BASE + 3, "PM3") +#define SUNXI_PINCTRL_PIN_PM4 PINCTRL_PIN(PM_BASE + 4, "PM4") +#define SUNXI_PINCTRL_PIN_PM5 PINCTRL_PIN(PM_BASE + 5, "PM5") +#define SUNXI_PINCTRL_PIN_PM6 PINCTRL_PIN(PM_BASE + 6, "PM6") +#define SUNXI_PINCTRL_PIN_PM7 PINCTRL_PIN(PM_BASE + 7, "PM7") +#define SUNXI_PINCTRL_PIN_PM8 PINCTRL_PIN(PM_BASE + 8, "PM8") +#define SUNXI_PINCTRL_PIN_PM9 PINCTRL_PIN(PM_BASE + 9, "PM9") +#define SUNXI_PINCTRL_PIN_PM10 PINCTRL_PIN(PM_BASE + 10, "PM10") +#define SUNXI_PINCTRL_PIN_PM11 PINCTRL_PIN(PM_BASE + 11, "PM11") +#define SUNXI_PINCTRL_PIN_PM12 PINCTRL_PIN(PM_BASE + 12, "PM12") +#define SUNXI_PINCTRL_PIN_PM13 PINCTRL_PIN(PM_BASE + 13, "PM13") +#define SUNXI_PINCTRL_PIN_PM14 PINCTRL_PIN(PM_BASE + 14, "PM14") +#define SUNXI_PINCTRL_PIN_PM15 PINCTRL_PIN(PM_BASE + 15, "PM15") +#define SUNXI_PINCTRL_PIN_PM16 PINCTRL_PIN(PM_BASE + 16, "PM16") +#define SUNXI_PINCTRL_PIN_PM17 PINCTRL_PIN(PM_BASE + 17, "PM17") +#define SUNXI_PINCTRL_PIN_PM18 PINCTRL_PIN(PM_BASE + 18, "PM18") +#define SUNXI_PINCTRL_PIN_PM19 PINCTRL_PIN(PM_BASE + 19, "PM19") +#define SUNXI_PINCTRL_PIN_PM20 PINCTRL_PIN(PM_BASE + 20, "PM20") +#define SUNXI_PINCTRL_PIN_PM21 PINCTRL_PIN(PM_BASE + 21, "PM21") +#define SUNXI_PINCTRL_PIN_PM22 PINCTRL_PIN(PM_BASE + 22, "PM22") +#define SUNXI_PINCTRL_PIN_PM23 PINCTRL_PIN(PM_BASE + 23, "PM23") +#define SUNXI_PINCTRL_PIN_PM24 PINCTRL_PIN(PM_BASE + 24, "PM24") +#define SUNXI_PINCTRL_PIN_PM25 PINCTRL_PIN(PM_BASE + 25, "PM25") +#define SUNXI_PINCTRL_PIN_PM26 PINCTRL_PIN(PM_BASE + 26, "PM26") +#define SUNXI_PINCTRL_PIN_PM27 PINCTRL_PIN(PM_BASE + 27, "PM27") +#define SUNXI_PINCTRL_PIN_PM28 PINCTRL_PIN(PM_BASE + 28, "PM28") +#define SUNXI_PINCTRL_PIN_PM29 PINCTRL_PIN(PM_BASE + 29, "PM29") +#define SUNXI_PINCTRL_PIN_PM30 PINCTRL_PIN(PM_BASE + 30, "PM30") +#define SUNXI_PINCTRL_PIN_PM31 PINCTRL_PIN(PM_BASE + 31, "PM31") + #define SUNXI_PIN_NAME_MAX_LEN 5 #define BANK_MEM_SIZE 0x24