From patchwork Fri Apr 11 18:01:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 3971751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5C23C9F370 for ; Fri, 11 Apr 2014 18:05:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E1FFC201B4 for ; Fri, 11 Apr 2014 18:05:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6AD902018A for ; Fri, 11 Apr 2014 18:05:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYfn8-0003jr-VK; Fri, 11 Apr 2014 18:03:06 +0000 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYfmr-0003P0-Kk for linux-arm-kernel@lists.infradead.org; Fri, 11 Apr 2014 18:02:50 +0000 Received: by mail-pa0-f41.google.com with SMTP id fa1so5746205pad.0 for ; Fri, 11 Apr 2014 11:02:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=QuoFpjn7jbwdlxaIz/o9vuv17w3HPbhX1bu8cKluZ18=; b=VBCBYLM9fUdKQ/U73H/I3hflrh0fv3gIsF4L5yJAA2R320y6t5rlV/RnGJg/JOL8Hj IN+tsAUTmwNCKBwqjbg9WxYm0pifNWeD73fWTrIfxIB2XJyCtsb9JnWzSvHxUpt4Ruzk BBuSUZ8yaFH33mhlu9DunONcrclFj/Qlcbh+hQBxMQaX1NGgvzV/ihj17sJis7QEFEPn uYfbcldgng/5pfSYXNnpTKRS6ssQ5DPZz6iM4g2kX9bM5j8il82ARr7zul9pExA7gFA4 6xhOL7TJzQTlumofBY/DLNTqF270VZUZZkPuTIDNZ+dBMgX9nIyUhirGIgsoec7EFWVO RV5A== X-Received: by 10.68.139.36 with SMTP id qv4mr29065271pbb.82.1397239349316; Fri, 11 Apr 2014 11:02:29 -0700 (PDT) Received: from localhost.localdomain ([122.171.66.111]) by mx.google.com with ESMTPSA id h6sm16993556pbl.75.2014.04.11.11.02.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 11 Apr 2014 11:02:28 -0700 (PDT) From: Abhilash Kesavan To: abrestic@chromium.org, thomas.ab@samsung.com, inderpal.s@samsung.com, lorenzo.pieralisi@arm.com, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, nicolas.pitre@linaro.org, Dave.Martin@arm.com, t.figa@samsung.com Subject: [PATCH 5/5] arm: exynos: Add MCPM call-back functions Date: Fri, 11 Apr 2014 23:31:51 +0530 Message-Id: <1397239311-27717-6-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1397239311-27717-1-git-send-email-a.kesavan@samsung.com> References: <1397239311-27717-1-git-send-email-a.kesavan@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140411_110249_731637_662E45D1 X-CRM114-Status: GOOD ( 27.45 ) X-Spam-Score: 0.0 (/) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, arnd@arndb.de, will.deacon@arm.com, robh+dt@kernel.org, grant.likely@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add machine-dependent MCPM call-backs for Exynos5420. These are used to power up/down the secondary CPUs during boot, shutdown, s2r and switching. Signed-off-by: Thomas Abraham Signed-off-by: Inderpal Singh Signed-off-by: Andrew Bresticker Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/Kconfig | 9 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/exynos.c | 1 + arch/arm/mach-exynos/mcpm-exynos-setup.S | 35 +++ arch/arm/mach-exynos/mcpm-exynos.c | 444 ++++++++++++++++++++++++++++++ arch/arm/mach-exynos/platsmp.c | 19 ++ arch/arm/mach-exynos/regs-pmu.h | 2 + 8 files changed, 513 insertions(+) create mode 100644 arch/arm/mach-exynos/mcpm-exynos-setup.S create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index fc8bf18..a921a80 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -110,4 +110,13 @@ config SOC_EXYNOS5440 endmenu +config EXYNOS5420_MCPM + bool "Exynos5420 Multi-Cluster PM support" + depends on MCPM && SOC_EXYNOS5420 + select ARM_CCI + help + Support for Dual Cluster Switching (A15/A7) on Exynos5420. + This is needed to provide CPU and cluster power management + on Exynos5420 implementing big.LITTLE. + endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index a656dbe..776fcbd 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS) += firmware.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) + +obj-$(CONFIG_EXYNOS5420_MCPM) += mcpm-exynos.o mcpm-exynos-setup.o diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 347afc2..a023ccc 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -51,6 +51,7 @@ static inline void exynos_pm_init(void) {} extern void exynos_cpu_resume(void); extern struct smp_operations exynos_smp_ops; +extern bool exynos_smp_init(void); extern void exynos_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index b1cf9d5..5b72b5e 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -412,6 +412,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") /* Maintainer: Thomas Abraham */ /* Maintainer: Kukjin Kim */ .smp = smp_ops(exynos_smp_ops), + .smp_init = smp_init_ops(exynos_smp_init), .map_io = exynos_init_io, .init_early = exynos_firmware_init, .init_machine = exynos_dt_machine_init, diff --git a/arch/arm/mach-exynos/mcpm-exynos-setup.S b/arch/arm/mach-exynos/mcpm-exynos-setup.S new file mode 100644 index 0000000..990c0d5 --- /dev/null +++ b/arch/arm/mach-exynos/mcpm-exynos-setup.S @@ -0,0 +1,35 @@ +/* + * Exynos low-level MCPM setup + * + * Copyright (C) 2013-2014 Google, Inc + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +ENTRY(exynos_power_up_setup) + + cmp r0, #0 @ check affinity level + beq 1f + +/* + * Enable cluster-level coherency, in preparation for turning on the MMU. + * The ACTLR SMP bit does not need to be set here, because cpu_resume() + * already restores that. + */ + b cci_enable_port_for_self + +1: @ Implementation-specific local CPU setup operations should go here, + @ if any. In this case, there is nothing to do. + + bx lr + +ENDPROC(exynos_power_up_setup) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c new file mode 100644 index 0000000..46d4968 --- /dev/null +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -0,0 +1,444 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * arch/arm/mach-exynos/mcpm-exynos.c + * + * Based on arch/arm/mach-vexpress/dcscb.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include "regs-pmu.h" + +#define EXYNOS5420_CPUS_PER_CLUSTER 4 +#define EXYNOS5420_NR_CLUSTERS 2 + +/* Secondary CPU entry point */ +#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1C) + +#define EXYNOS_CORE_LOCAL_PWR_EN 0x3 +#define EXYNOS_CORE_LOCAL_PWR_DIS 0x0 + +#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500) +#define EXYNOS_ARM_L2_CONFIGURATION S5P_PMUREG(0x2600) + +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ + (S5P_ARM_CORE0_CONFIGURATION + ((_nr) * 0x80)) +#define EXYNOS_ARM_CORE_STATUS(_nr) \ + (S5P_ARM_CORE0_STATUS + ((_nr) * 0x80)) + +#define EXYNOS_COMMON_CONFIGURATION(_nr) \ + (EXYNOS_ARM_COMMON_CONFIGURATION + ((_nr) * 0x80)) +#define EXYNOS_COMMON_STATUS(_nr) \ + (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) + +#define EXYNOS_L2_CONFIGURATION(_nr) \ + (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) +#define EXYNOS_L2_STATUS(_nr) \ + (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) + +/* + * We can't use regular spinlocks. In the switcher case, it is possible + * for an outbound CPU to call power_down() after its inbound counterpart + * is already live using the same logical CPU number which trips lockdep + * debugging. + */ +static arch_spinlock_t bl_lock = __ARCH_SPIN_LOCK_UNLOCKED; +static int +cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS]; + +static bool exynos_core_power_state(unsigned int cpu, unsigned int cluster) +{ + unsigned int val; + unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + + val = __raw_readl(EXYNOS_ARM_CORE_STATUS(cpunr)) & + EXYNOS_CORE_LOCAL_PWR_EN; + return !!val; +} + +static void exynos_core_power_control(unsigned int cpu, unsigned int cluster, + int enable) +{ + unsigned int val = EXYNOS_CORE_LOCAL_PWR_DIS; + unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + + if (exynos_core_power_state(cpu, cluster) == enable) + return; + + if (enable) + val = EXYNOS_CORE_LOCAL_PWR_EN; + __raw_writel(val, EXYNOS_ARM_CORE_CONFIGURATION(cpunr)); +} + +static void exynos_cluster_power_control(unsigned int cluster, int enable) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(20); + unsigned int status, val = EXYNOS_CORE_LOCAL_PWR_DIS; + + if (enable) + val = EXYNOS_CORE_LOCAL_PWR_EN; + + status = __raw_readl(EXYNOS_COMMON_STATUS(cluster)); + if ((status & EXYNOS_CORE_LOCAL_PWR_EN) == val) + return; + + __raw_writel(val, EXYNOS_COMMON_CONFIGURATION(cluster)); + /* Wait until cluster power control is applied */ + while (time_before(jiffies, timeout)) { + status = __raw_readl(EXYNOS_COMMON_STATUS(cluster)); + + if ((status & EXYNOS_CORE_LOCAL_PWR_EN) == val) + return; + + cpu_relax(); + } + pr_warn("timed out waiting for cluster %u to power %s\n", cluster, + enable ? "on" : "off"); +} + +static int exynos_power_up(unsigned int cpu, unsigned int cluster) +{ + unsigned long mpidr; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || + cluster >= EXYNOS5420_NR_CLUSTERS) + return -EINVAL; + + /* + * Since this is called with IRQs enabled, and no arch_spin_lock_irq + * variant exists, we need to disable IRQs manually here. + */ + local_irq_disable(); + arch_spin_lock(&bl_lock); + + cpu_use_count[cpu][cluster]++; + if (cpu_use_count[cpu][cluster] == 1) { + bool was_cluster_down = + __mcpm_cluster_state(cluster) == CLUSTER_DOWN; + + if (was_cluster_down) + exynos_cluster_power_control(cluster, 1); + exynos_core_power_control(cpu, cluster, 1); + + if (was_cluster_down) { + mpidr = read_cpuid_mpidr(); + udelay(10); + cci_control_port_by_cpu(mpidr, true); + } + + /* CPU should be powered up there */ + /* Also setup Cluster Power Sequence here */ + } else if (cpu_use_count[cpu][cluster] != 2) { + /* + * The only possible values are: + * 0 = CPU down + * 1 = CPU (still) up + * 2 = CPU requested to be up before it had a chance + * to actually make itself down. + * Any other value is a bug. + */ + BUG(); + } + + arch_spin_unlock(&bl_lock); + local_irq_enable(); + + return 0; +} + +static void exynos_power_down(void) +{ + unsigned int mpidr, cpu, cluster, cpumask; + bool last_man = false, skip_wfi = false; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + cpumask = (1 << cpu); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || + cluster >= EXYNOS5420_NR_CLUSTERS); + + __mcpm_cpu_going_down(cpu, cluster); + + arch_spin_lock(&bl_lock); + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); + cpu_use_count[cpu][cluster]--; + if (cpu_use_count[cpu][cluster] == 0) { + int cnt = 0, i; + + exynos_core_power_control(cpu, cluster, 0); + for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++) + cnt += cpu_use_count[i][cluster]; + if (cnt == 0) + last_man = true; + } else if (cpu_use_count[cpu][cluster] == 1) { + /* + * A power_up request went ahead of us. + * Even if we do not want to shut this CPU down, + * the caller expects a certain state as if the WFI + * was aborted. So let's continue with cache cleaning. + */ + skip_wfi = true; + } else { + BUG(); + } + + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { + arch_spin_unlock(&bl_lock); + + /* + * Flush all cache levels for this cluster. + * + * To do so we do: + * - Clear the SCTLR.C bit to prevent further cache allocations + * - Flush the whole cache + * - Clear the ACTLR "SMP" bit to disable local coherency + * + * Let's do it in the safest possible way i.e. with + * no memory access within the following sequence + * including to the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. + * + * The common v7_exit_coherency_flush API that could not be + * used because of the Erratum 799270 workaround. + */ + asm volatile( + "stmfd sp!, {fp, ip}\n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" + "bic r0, r0, #"__stringify(CR_C)"\n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" + "isb\n\t" + "bl v7_flush_dcache_all\n\t" + "clrex\n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" + /* Dummy Load of a device register to avoid Erratum 799270 */ + "ldr r4, [%0]\n\t" + "and r4, r4, #0\n\t" + "orr r0, r0, r4\n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" + "isb\n\t" + "dsb\n\t" + "ldmfd sp!, {fp, ip}" + : + : "Ir" (S5P_INFORM0) + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r9", "r10", "lr", "memory"); + + /* + * This is a harmless no-op. On platforms with a real + * outer cache this might either be needed or not, + * depending on where the outer cache sits. + */ + outer_flush_all(); + + /* + * Disable cluster-level coherency by masking + * incoming snoops and DVM messages: + */ + cci_control_port_by_cpu(mpidr, false); + cci_control_port_by_cpu(mpidr ^ (1 << 8), false); + + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); + } else { + arch_spin_unlock(&bl_lock); + + /* + * Flush the local CPU cache. + * Let's do it in the safest possible way as above. + */ + asm volatile( + "stmfd sp!, {fp, ip}\n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" + "bic r0, r0, #"__stringify(CR_C)"\n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" + "isb\n\t" + "bl v7_flush_dcache_louis\n\t" + "clrex\n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" + /* Dummy Load of a device register to avoid Erratum 799270 */ + "ldr r4, [%0]\n\t" + "and r4, r4, #0\n\t" + "orr r0, r0, r4\n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" + "isb\n\t" + "dsb\n\t" + "ldmfd sp!, {fp, ip}" + : + : "Ir" (S5P_INFORM0) + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r9", "r10", "lr", "memory"); + } + + __mcpm_cpu_down(cpu, cluster); + + /* Now we are prepared for power-down, do it: */ + dsb(); + if (!skip_wfi) + wfi(); + + /* Not dead at this point? Let our caller cope. */ +} + +static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster) +{ + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || + cluster >= EXYNOS5420_NR_CLUSTERS); + + /* Wait for the core state to be OFF */ + while (exynos_core_power_state(cpu, cluster) != 0x0) + ; + + return 0; /* success: the CPU is halted */ +} + +static const struct mcpm_platform_ops exynos_power_ops = { + .power_up = exynos_power_up, + .power_down = exynos_power_down, + .power_down_finish = exynos_power_down_finish, +}; + +static void __init exynos_mcpm_usage_count_init(void) +{ + unsigned int mpidr, cpu, cluster, i; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || + cluster >= EXYNOS5420_NR_CLUSTERS); + + for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++) { + cpu_use_count[i][0] = 0; + cpu_use_count[i][1] = 0; + } + cpu_use_count[cpu][cluster] = 1; +} + +static size_t bL_check_status(char *info) +{ + size_t len = 0; + int i; + + len += sprintf(&info[len], "\t0 1 2 3 L2\n"); + len += sprintf(&info[len], "[A15] "); + for (i = 0; i < 4; i++) { + len += sprintf(&info[len], "%d ", + (readl(EXYNOS_ARM_CORE_STATUS(i)) & 0x3) == 3 ? 1 : 0); + } + len += sprintf(&info[len], "%d\n", + (readl(EXYNOS_COMMON_STATUS(0)) & 0x3) == 3 ? 1 : 0); + + len += sprintf(&info[len], "[A7] "); + for (i = 4; i < 8; i++) + len += sprintf(&info[len], "%d ", + (readl(EXYNOS_ARM_CORE_STATUS(i)) & 0x3) == 3 ? 1 : 0); + len += sprintf(&info[len], "%d\n\n", + (readl(EXYNOS_COMMON_STATUS(1)) & 0x3) == 3 ? 1 : 0); + + return len; +} + +static ssize_t bL_status_read(struct file *file, char __user *buf, + size_t len, loff_t *pos) +{ + size_t count = 0; + char info[100]; + + count = bL_check_status(info); + if (count < 0) + return -EINVAL; + + return simple_read_from_buffer(buf, len, pos, info, count); +} + +static const struct file_operations bL_status_fops = { + .read = bL_status_read, +}; + +static struct miscdevice bL_status_device = { + MISC_DYNAMIC_MINOR, + "bL_status", + &bL_status_fops +}; + +extern void exynos_power_up_setup(unsigned int affinity_level); + +static int __init exynos_mcpm_init(void) +{ + int ret = 0; + + if (!cci_probed()) + return -ENODEV; + + if (!soc_is_exynos5420()) + return 0; + + /* + * To increase the stability of KFC reset we need to program + * the PMU SPARE3 register + */ + __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); + + exynos_mcpm_usage_count_init(); + + ret = mcpm_platform_register(&exynos_power_ops); + if (!ret) + ret = mcpm_sync_init(exynos_power_up_setup); + + pr_info("Exynos MCPM support installed\n"); + + /* + * Future entries into the kernel can now go + * through the cluster entry vectors. + */ + __raw_writel(virt_to_phys(mcpm_entry_point), + REG_ENTRY_ADDR); + + return ret; +} + +early_initcall(exynos_mcpm_init); + +static int __init exynos_bl_status_init(void) +{ + int ret; + + if (!soc_is_exynos5420()) + return 0; + + ret = misc_register(&bL_status_device); + if (ret) + pr_info("bl_status not available\n"); + return 0; +} + +late_initcall(exynos_bl_status_init); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 03e5e9f..4f14457 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -226,6 +227,24 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) } } +bool __init exynos_smp_init(void) +{ +#ifdef CONFIG_MCPM + /* + * The best way to detect a multi-cluster configuration at the moment + * is to look for the presence of a CCI in the system. + * Override the default exynos_smp_ops if so. + */ + struct device_node *node; + node = of_find_compatible_node(NULL, NULL, "arm,cci-400"); + if (node && of_device_is_available(node)) { + mcpm_smp_set_ops(); + return true; + } +#endif + return false; +} + struct smp_operations exynos_smp_ops __initdata = { .smp_init_cpus = exynos_smp_init_cpus, .smp_prepare_cpus = exynos_smp_prepare_cpus, diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index cfbfc575..43fe7a0 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -38,6 +38,7 @@ #define S5P_INFORM5 S5P_PMUREG(0x0814) #define S5P_INFORM6 S5P_PMUREG(0x0818) #define S5P_INFORM7 S5P_PMUREG(0x081C) +#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C) #define EXYNOS_IROM_DATA2 S5P_PMUREG(0x0988) @@ -540,5 +541,6 @@ #define EXYNOS5420_KFC_USE_STANDBY_WFE3 (1 << 23) #define DUR_WAIT_RESET 0xF +#define EXYNOS5420_SWRESET_KFC_SEL 0x3 #endif /* __ASM_ARCH_REGS_PMU_H */