| Message ID | 1397497283-16391-5-git-send-email-ivan.khoronzhuk@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 90823eb..9d6b850 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -69,7 +69,9 @@ rstctrl: reset-controller { compatible = "ti,keystone-reset"; - reg = <0x023100e8 4>; /* pll reset control reg */ + reg = <0x23100e4 0x10>, <0x2620328 0x10>; + reg-names = "pllregs", "muxregs"; + ti,wdt_list = <0>; }; /include/ "keystone-clocks.dtsi"
The reset controller registers are part of the PLL Controller MMRs. According to TRM there are the following registers: RSTYPE, RSCTRL, RSCFG and RSISO. Currently declared only one of them, but that is not enough to correctly setup reset properties, so add whole range of pll registers - pllregs. Also add range for reset multiplex registers for SoC on the device. These registers are located in Bootcfg memory space and needed to setup behaviour after appropriate watchdog is triggered. Add "ti,wdt_list" option to declare what watchdog are used to reboot the SoC. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- arch/arm/boot/dts/keystone.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)