From patchwork Tue Apr 15 01:42:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 3988281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9EBDE9F2CC for ; Tue, 15 Apr 2014 01:46:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D8432201F9 for ; Tue, 15 Apr 2014 01:46:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 14258201DE for ; Tue, 15 Apr 2014 01:46:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WZsPC-0003y3-Ss; Tue, 15 Apr 2014 01:43:22 +0000 Received: from mail-pb0-f73.google.com ([209.85.160.73]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WZsP4-0003tZ-Tb for linux-arm-kernel@lists.infradead.org; Tue, 15 Apr 2014 01:43:15 +0000 Received: by mail-pb0-f73.google.com with SMTP id rp16so1145632pbb.2 for ; Mon, 14 Apr 2014 18:42:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7rUXcrCZpWiMrjW5mECbHYWcCC6Cct9yxf3PByl9Lw8=; b=OW5cOD27wI9zjOVbDLFin0CEgXmiKZfOOEKdgIg9BPOkdZLgrrIHi1J1KsYL2kLQXV GY8hI0e3mT8WTFJwOgDEA4QFMb/93h0T2QNPoT6cW5DKWBgFmc6BvRbKHCB3as4+6z9/ IgN7ld9s8+2pfVe2hFnBKC3MmCavmWxn5hv2IdrFsxroCNRV2+boZ4BG7p2kv5XtFc/0 r3k7blbTQkn9nKvfjOt/ySMcmF2+j4VkHy37iQhbZXo5FhMV19kXTEJaLLX1jIV9CrzI fg9ZqS0ik5/LNq8w2hF3234heuTgMYJZOzKUE6tyHEoGas/KNKESDgVZ+7iQgf2pSwgs iXYg== X-Gm-Message-State: ALoCoQm2JvVMSnMJpqKyQAyFDVhJ9Y5a6t1rTYea2qXRwZoIZlhqHmH4jR9TRqfoQGUQ3ZWWJOkciuyLJNbHYcqmkxi6deVxeQrt59BltbSCLpru3/PLsFy4q2u1Wwy1arN+SOrfPm9Y4g0as0UcJslDzwY+zkIAByKunjM7sgDSok8ySF7sodfZ3066ELPTvMeFO59HUV2xxINq2mCjeOYXsxHS5nS92g== X-Received: by 10.66.232.38 with SMTP id tl6mr12766978pac.33.1397526173284; Mon, 14 Apr 2014 18:42:53 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id e40si2521631yhf.0.2014.04.14.18.42.53 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Apr 2014 18:42:53 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 12A9F31C1E3; Mon, 14 Apr 2014 18:42:53 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id CA9DA220757; Mon, 14 Apr 2014 18:42:52 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , Chris Ball , Ulf Hansson Subject: [PATCH 2/4] mmc: tegra: fix reporting of base clock frequency Date: Mon, 14 Apr 2014 18:42:41 -0700 Message-Id: <1397526163-20126-3-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1397526163-20126-1-git-send-email-abrestic@chromium.org> References: <1397526163-20126-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140414_184314_970777_CB3E0873 X-CRM114-Status: GOOD ( 11.90 ) X-Spam-Score: -1.7 (-) Cc: linux-tegra@vger.kernel.org, Andrew Bresticker , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base clock frequency. While this can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and supply a get_max_clock() callback to get the actual rate of the base clock. Signed-off-by: Andrew Bresticker --- drivers/mmc/host/sdhci-tegra.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 3cadd9c..c3f92d9 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -165,13 +165,15 @@ static const struct sdhci_ops tegra_sdhci_ops = { .write_l = tegra_sdhci_writel, .platform_bus_width = tegra_sdhci_buswidth, .platform_reset_exit = tegra_sdhci_reset_exit, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, }; static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -186,7 +188,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -202,7 +205,8 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, };