From patchwork Wed Apr 16 20:14:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 4003961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AD271BFF02 for ; Wed, 16 Apr 2014 20:20:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D021420306 for ; Wed, 16 Apr 2014 20:20:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BCDC02034C for ; Wed, 16 Apr 2014 20:20:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WaWGn-0007oQ-7w; Wed, 16 Apr 2014 20:17:21 +0000 Received: from mail-bn1bn0107.outbound.protection.outlook.com ([157.56.110.107] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WaWGj-0007nH-Hw for linux-arm-kernel@lists.infradead.org; Wed, 16 Apr 2014 20:17:18 +0000 Received: from BN1BFFO11FD019.protection.gbl (10.58.144.32) by BN1BFFO11HUB005.protection.gbl (10.58.144.152) with Microsoft SMTP Server (TLS) id 15.0.918.6; Wed, 16 Apr 2014 20:16:53 +0000 Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by BN1BFFO11FD019.mail.protection.outlook.com (10.58.144.82) with Microsoft SMTP Server (TLS) id 15.0.918.6 via Frontend Transport; Wed, 16 Apr 2014 20:16:53 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.348.2; Wed, 16 Apr 2014 13:03:34 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s3GKGmuD018392; Wed, 16 Apr 2014 13:16:50 -0700 (PDT) From: To: , Subject: [PATCH 2/2] ARM: socfpga: dts: Add div-reg to the main_pll clocks Date: Wed, 16 Apr 2014 15:14:30 -0500 Message-ID: <1397679270-29695-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1397679270-29695-1-git-send-email-dinguyen@altera.com> References: <1397679270-29695-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019001)(6009001)(458001)(189002)(199002)(48376002)(19580395003)(80976001)(83322001)(19580405001)(87936001)(76482001)(88136002)(84676001)(44976005)(50226001)(77156001)(81542001)(81342001)(53416003)(80022001)(4396001)(6806004)(31966008)(74662001)(36756003)(87286001)(92726001)(86362001)(83072002)(20776003)(33646001)(89996001)(74502001)(93916002)(92566001)(86152002)(97736001)(79102001)(85852003)(50466002)(77982001)(46102001)(47776003)(62966002)(99396002)(2009001)(50986999)(76176999); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1BFFO11HUB005; H:SJ-ITEXEDGE02.altera.priv.altera.com; FPR:6A6ABA5C.C81E8F2E.73D38087.40C7D6C9.2023B; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 01834E39B7 Received-SPF: SoftFail (: domain of transitioning altera.com discourages use of 66.35.236.232 as permitted sender) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140416_131717_802891_A32C56A2 X-CRM114-Status: UNSURE ( 9.39 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: s.trumtrar@pengutronix.de, Dinh Nguyen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/clock/altr_socfpga.txt | 4 ++-- arch/arm/boot/dts/socfpga.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 5dfd145..f72e80e 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -21,8 +21,8 @@ Optional properties: - fixed-divider : If clocks have a fixed divider value, use this property. - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register and the bit index. -- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, - and width. +- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains + the divider register, bit shift, and width. - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 56fc214..291eff1 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -124,7 +124,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <2>; + div-reg = <0xe0 0 9>; reg = <0x48>; }; @@ -132,7 +132,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <4>; + div-reg = <0xe4 0 9>; reg = <0x4C>; }; @@ -140,7 +140,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <4>; + div-reg = <0xe8 0 9>; reg = <0x50>; };