From patchwork Tue Apr 22 18:31:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Fernandes X-Patchwork-Id: 4034091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4BD449F1F4 for ; Tue, 22 Apr 2014 18:35:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B99A201EF for ; Tue, 22 Apr 2014 18:35:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6D6C200DB for ; Tue, 22 Apr 2014 18:35:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcfVA-0004CT-SC; Tue, 22 Apr 2014 18:33:04 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcfUl-0003ks-5R for linux-arm-kernel@lists.infradead.org; Tue, 22 Apr 2014 18:32:39 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3MIWA1a018553; Tue, 22 Apr 2014 13:32:10 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3MIWAct031830; Tue, 22 Apr 2014 13:32:10 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 22 Apr 2014 13:32:10 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3MIWAZi004477; Tue, 22 Apr 2014 13:32:10 -0500 Received: from joel-laptop.am.dhcp.ti.com (joel-laptop.am.dhcp.ti.com [128.247.71.194]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3MIW9t15944; Tue, 22 Apr 2014 13:32:09 -0500 (CDT) From: Joel Fernandes To: Linux OMAP List , Linux ARM Kernel List , Linux Kernel Mailing List Subject: [PATCH] ARM: OMAP5: Switch to THUMB mode if needed on secondary CPU Date: Tue, 22 Apr 2014 13:31:46 -0500 Message-ID: <1398191506-3741-1-git-send-email-joelf@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140422_113239_336828_B1A9161C X-CRM114-Status: GOOD ( 15.07 ) X-Spam-Score: -5.7 (-----) Cc: Joel Fernandes , Russell King , Nishanth Menon , Santosh Shilimkar , Tony Lindgren X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This seems to be because the CPU is in ARM mode once the ROM hands over control to the kernel. Switch to THUMB mode if required once the kernel is control of secondary CPU. On OMAP4 on the other hand, it appears to be in THUMB mode on entry so this is not required and SMP boot works as is. Cc: Santosh Shilimkar Cc: Russell King Cc: Nishanth Menon Cc: Tony Lindgren Signed-off-by: Joel Fernandes Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap-headsmp.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 75e9295..1809dce 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -1,7 +1,7 @@ /* * Secondary CPU startup routine source file. * - * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2014 Texas Instruments, Inc. * * Author: * Santosh Shilimkar @@ -28,9 +28,13 @@ * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. * The primary core will update this flag using a hardware -+ * register AuxCoreBoot0. + * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) +.arm +THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. +THUMB( bx r9 ) @ If this is a Thumb-2 kernel, +THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5