From patchwork Thu Apr 24 20:23:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 4053871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A1FB79F319 for ; Thu, 24 Apr 2014 20:27:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C5E7C201F7 for ; Thu, 24 Apr 2014 20:27:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EF9520295 for ; Thu, 24 Apr 2014 20:27:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WdQBw-0007FL-JF; Thu, 24 Apr 2014 20:24:20 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WdQBs-00078a-RZ for linux-arm-kernel@lists.infradead.org; Thu, 24 Apr 2014 20:24:18 +0000 Received: from dude.hi.pengutronix.de ([10.1.0.7] helo=dude.pengutronix.de) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1WdQBQ-00022f-2u; Thu, 24 Apr 2014 22:23:48 +0200 From: Lucas Stach To: Shawn Guo Subject: [PATCH] ARM: imx6q: work around faulty PMU irq routing Date: Thu, 24 Apr 2014 22:23:49 +0200 Message-Id: <1398371029-21176-1-git-send-email-l.stach@pengutronix.de> X-Mailer: git-send-email 1.9.1 X-SA-Exim-Connect-IP: 10.1.0.7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140424_132417_337742_521FECCF X-CRM114-Status: GOOD ( 15.02 ) X-Spam-Score: -0.7 (/) Cc: kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The i.MX6 PMU has a design errata where the interrupts of all cores are wired together into a single irq line. To work around this we have to bounce the interrupt around all cores until we find the one where the PMU counter overflow has happened. This causes the perf measurements to be less accurate and we can't really handle the case where two cores fire a PMU irq at the same time. The implemented woraround makes perf at least somewhat useable on imx6 SoCs with more than one core. Signed-off-by: Lucas Stach --- arch/arm/mach-imx/mach-imx6q.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index e60456d85c9d..73976c484826 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -16,6 +16,7 @@ #include #include #include +#include "linux/interrupt.h" #include #include #include @@ -33,6 +34,7 @@ #include #include #include +#include "asm/pmu.h" #include #include "common.h" @@ -261,6 +263,39 @@ static void __init imx6q_axi_init(void) } } +/* + * The i.MX6 PMU has a design errata where the interrupts of all cores are + * wired together into a single irq line. To work around this we have to + * bounce the interrupt around all cores until we find the one where the PMU + * counter overflow has happened. + */ +static irqreturn_t imx6q_pmu_handler(int irq, void *dev, irq_handler_t handler) +{ + irqreturn_t ret = handler(irq, dev); + int next; + + if (ret == IRQ_NONE) { + /* + * Kick the irq over to the next cpu, regardless of it's + * online status (it might have gone offline while we were busy + * bouncing the irq). + */ + next = (smp_processor_id() + 1) % num_present_cpus(); + irq_set_affinity(irq, cpumask_of(next)); + } + + return ret; +} + +struct arm_pmu_platdata imx6q_pmu_platdata = { + .handle_irq = imx6q_pmu_handler, +}; + +static struct of_dev_auxdata imx6q_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &imx6q_pmu_platdata), + {} +}; + static void __init imx6q_init_machine(void) { struct device *parent; @@ -276,7 +311,8 @@ static void __init imx6q_init_machine(void) imx6q_enet_phy_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); + of_platform_populate(NULL, of_default_bus_match_table, + imx6q_auxdata_lookup, parent); imx_anatop_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();