From patchwork Mon May 5 15:53:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 4115861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 134509F1E1 for ; Mon, 5 May 2014 15:57:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 296EC2022D for ; Mon, 5 May 2014 15:57:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3942820251 for ; Mon, 5 May 2014 15:57:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhLFH-0002t6-0k; Mon, 05 May 2014 15:55:59 +0000 Received: from mx07-00178001.pphosted.com ([62.209.51.94]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhLEK-00017k-Qh for linux-arm-kernel@lists.infradead.org; Mon, 05 May 2014 15:55:02 +0000 Received: from pps.filterd (m0046670.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s45FoLcd032382; Mon, 5 May 2014 17:54:17 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 1kkyd0r1kq-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Mon, 05 May 2014 17:54:17 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9E59263; Mon, 5 May 2014 15:54:05 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5550B16901; Mon, 5 May 2014 15:54:05 +0000 (GMT) Received: from lmenx315.lme.st.com ([10.201.19.41]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZG03559 (AUTH frq07381); Mon, 5 May 2014 17:54:04 +0200 From: Gabriel FERNANDEZ To: Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King Subject: [PATCH 4/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F Date: Mon, 5 May 2014 17:53:38 +0200 Message-Id: <1399305223-18703-5-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1399305223-18703-1-git-send-email-gabriel.fernandez@linaro.org> References: <1399305223-18703-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.11.96, 1.0.14, 0.0.0000 definitions=2014-05-05_02:2014-05-05, 2014-05-05, 1970-01-01 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140505_085501_259883_011BAEF9 X-CRM114-Status: UNSURE ( 9.50 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.6 (/) Cc: devicetree@vger.kernel.org, kernel@stlinux.com, linux-kernel@vger.kernel.org, Pankaj Dev , linux-arm-kernel@lists.infradead.org, Lee Jones , Gabriel Fernandez X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,GAPPY_SUBJECT, RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Patch adds DT entries for clockgen B/C/D/E/F Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez --- arch/arm/boot/dts/stih416-clock.dtsi | 189 +++++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi index fdb5654..7ff107b 100644 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ b/arch/arm/boot/dts/stih416-clock.dtsi @@ -503,5 +503,194 @@ /* Remaining outputs unused */ }; }; + + /* + * Frequency synthesizers on the SASG2 + */ + CLOCKGEN_B0: CLOCKGEN_B0 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee108b4 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_USB48", + "CLK_S_DSS", + "CLK_S_STFE_FRC_2", + "CLK_S_THSENS_SCARD"; + }; + + CLOCKGEN_B1: CLOCKGEN_B1 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfe8308c4 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_PCM_0", + "CLK_S_PCM_1", + "CLK_S_PCM_2", + "CLK_S_PCM_3"; + }; + + CLOCKGEN_C: CLOCKGEN_C { + #clock-cells = <1>; + compatible = "st,stih416-quadfs432", "st,quadfs"; + reg = <0xfe8307d0 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_C_FS0_CH0", + "CLK_S_C_VCC_SD", + "CLK_S_C_FS0_CH2"; + }; + + CLK_S_VCC_HD: CLK_S_VCC_HD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; + reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ + + clocks = <&CLK_SYSIN>, + <&CLOCKGEN_C 0>; + }; + + /* + * Add a dummy clock for the HDMI PHY for the VCC input mux + */ + CLK_S_TMDS_FROMPHY: CLK_S_TMDS_FROMPHY { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + CLOCKGEN_C_VCC: CLOCKGEN_C_VCC { + #clock-cells = <1>; + compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; + reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ + + clocks = <&CLK_S_VCC_HD>, + <&CLOCKGEN_C 1>, + <&CLK_S_TMDS_FROMPHY>, + <&CLOCKGEN_C 2>; + + clock-output-names = "CLK_S_PIX_HDMI", + "CLK_S_PIX_DVO", + "CLK_S_OUT_DVO", + "CLK_S_PIX_HD", + "CLK_S_HDDAC", + "CLK_S_DENC", + "CLK_S_SDDAC", + "CLK_S_PIX_MAIN", + "CLK_S_PIX_AUX", + "CLK_S_STFE_FRC_0", + "CLK_S_REF_MCRU", + "CLK_S_SLAVE_MCRU", + "CLK_S_TMDS_HDMI", + "CLK_S_HDMI_REJECT_PLL", + "CLK_S_THSENS"; + }; + + CLOCKGEN_D: CLOCKGEN_D { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee107e0 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_CCSC", + "CLK_S_STFE_FRC_1", + "CLK_S_TSOUT_1", + "CLK_S_MCHI"; + }; + + /* + * Frequency synthesizers on the MPE42 + */ + CLOCKGEN_E: CLOCKGEN_E { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-E", "st,quadfs"; + reg = <0xfd3208bc 0xb0>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_M_PIX_MDTP_0", + "CLK_M_PIX_MDTP_1", + "CLK_M_PIX_MDTP_2", + "CLK_M_MPELPC"; + }; + + CLOCKGEN_F: CLOCKGEN_F { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-F", "st,quadfs"; + reg = <0xfd320878 0xf0>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_M_MAIN_VIDFS", + "CLK_M_HVA_FS", + "CLK_M_FVDP_VCPU", + "CLK_M_FVDP_PROC_FS"; + }; + + CLK_M_FVDP_PROC: CLK_M_FVDP_PROC { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; + reg = <0xfd320910 0x4>; /* SYSCFG8580 */ + + clocks = <&CLK_M_A1_DIV2 0>, + <&CLOCKGEN_F 3>; + }; + + CLK_M_HVA: CLK_M_HVA { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; + reg = <0xfd690868 0x4>; /* SYSCFG9538 */ + + clocks = <&CLOCKGEN_F 1>, + <&CLK_M_A1_DIV0 3>; + }; + + CLK_M_F_VCC_HD: CLK_M_F_VCC_HD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&CLOCKGEN_C_VCC 7>, + <&CLOCKGEN_F 0>; + }; + + CLK_M_F_VCC_SD: CLK_M_F_VCC_SD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&CLOCKGEN_C_VCC 8>, + <&CLOCKGEN_F 1>; + }; + + /* + * Add a dummy clock for the HDMIRx external signal clock + */ + CLK_M_PIX_HDMIRX_SAS: CLK_M_PIX_HDMIRX_SAS { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + CLOCKGEN_F_VCC: CLOCKGEN_F_VCC { + #clock-cells = <1>; + compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; + reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ + + clocks = <&CLK_M_F_VCC_HD>, + <&CLK_M_F_VCC_SD>, + <&CLOCKGEN_F 0>, + <&CLK_M_PIX_HDMIRX_SAS>; + + clock-output-names = "CLK_M_PIX_MAIN_PIPE", + "CLK_M_PIX_AUX_PIPE", + "CLK_M_PIX_MAIN_CRU", + "CLK_M_PIX_AUX_CRU", + "CLK_M_XFER_BE_COMPO", + "CLK_M_XFER_PIP_COMPO", + "CLK_M_XFER_AUX_COMPO", + "CLK_M_VSENS", + "CLK_M_PIX_HDMIRX_0", + "CLK_M_PIX_HDMIRX_1"; + }; }; };