From patchwork Tue May 6 13:33:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 4121511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AB5A6BFF02 for ; Tue, 6 May 2014 13:38:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BDDAF201ED for ; Tue, 6 May 2014 13:38:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B5DC5201EC for ; Tue, 6 May 2014 13:38:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhfWp-0004AH-Pp; Tue, 06 May 2014 13:35:27 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhfWS-0002k1-Jc for linux-arm-kernel@lists.infradead.org; Tue, 06 May 2014 13:35:05 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s46DYfPt011653; Tue, 6 May 2014 08:34:41 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s46DYfZu031807; Tue, 6 May 2014 08:34:41 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 6 May 2014 08:34:40 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s46DYE8S031249; Tue, 6 May 2014 08:34:37 -0500 From: Kishon Vijay Abraham I To: , , , , , Subject: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY Date: Tue, 6 May 2014 19:03:49 +0530 Message-ID: <1399383244-14556-4-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399383244-14556-1-git-send-email-kishon@ti.com> References: <1399383244-14556-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140506_063504_808195_A5CB07DC X-CRM114-Status: GOOD ( 13.22 ) X-Spam-Score: -5.7 (-----) Cc: Paul Walmsley , balajitk@ti.com, Rajendra Nayak , Kishon Vijay Abraham I , Tero Kristo , rogerq@ti.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP APLL used by PCIE phy can either use external clock as input or the clock from DPLL. Added support for the APLL to use external clock as input here. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++ drivers/phy/phy-ti-pipe3.c | 75 ++++++++++++++-------- 2 files changed, 52 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index bc9afb5..d50f8ee 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -76,6 +76,10 @@ Required properties: * "dpll_ref_m2" - external dpll ref clk * "phy-div" - divider for apll * "div-clk" - apll clock + * "apll_mux" - mux for pcie apll + * "refclk_ext" - external reference clock for pcie apll + - ti,ext-clk: To specifiy if PCIE apll should use external clock. Applicable + only to PCIE PHY. Optional properties: - ctrl-module : phandle of the control module used by PHY driver to power on diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index d43019d..5513aa0 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -293,7 +293,7 @@ static int ti_pipe3_probe(struct platform_device *pdev) struct device_node *control_node; struct platform_device *control_pdev; const struct of_device_id *match; - struct clk *clk; + struct clk *clk, *pclk; phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); if (!phy) { @@ -302,6 +302,20 @@ static int ti_pipe3_probe(struct platform_device *pdev) } phy->dev = &pdev->dev; + control_node = of_parse_phandle(node, "ctrl-module", 0); + if (!control_node) { + dev_err(&pdev->dev, "Failed to get control device phandle\n"); + return -EINVAL; + } + + control_pdev = of_find_device_by_node(control_node); + if (!control_pdev) { + dev_err(&pdev->dev, "Failed to get control device\n"); + return -EINVAL; + } + + phy->control_dev = &control_pdev->dev; + if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev); @@ -345,19 +359,40 @@ static int ti_pipe3_probe(struct platform_device *pdev) } if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { - clk = devm_clk_get(phy->dev, "dpll_ref"); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "unable to get dpll ref clk\n"); - return PTR_ERR(clk); + if (!of_property_read_bool(node, "ti,ext-clk")) { + clk = devm_clk_get(phy->dev, "dpll_ref"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, + "unable to get dpll ref clk\n"); + return PTR_ERR(clk); + } + clk_set_rate(clk, 1500000000); + + clk = devm_clk_get(phy->dev, "dpll_ref_m2"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, + "unable to get dpll ref m2 clk\n"); + return PTR_ERR(clk); + } + clk_set_rate(clk, 100000000); + } else { + omap_control_pcie_tx_rx_control(phy->control_dev, + OMAP_CTRL_PCIE_PHY_RX_ACSPCIE); + + clk = clk_get(phy->dev, "apll_mux"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "unable to get apll mux clk\n"); + return PTR_ERR(clk); + } + + pclk = clk_get(phy->dev, "refclk_ext"); + if (IS_ERR(pclk)) { + dev_err(&pdev->dev, "unable to get ext ref clk for apll\n"); + return PTR_ERR(pclk); + } + + clk_set_parent(clk, pclk); } - clk_set_rate(clk, 1500000000); - - clk = devm_clk_get(phy->dev, "dpll_ref_m2"); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n"); - return PTR_ERR(clk); - } - clk_set_rate(clk, 100000000); clk = devm_clk_get(phy->dev, "phy-div"); if (IS_ERR(clk)) { @@ -375,20 +410,6 @@ static int ti_pipe3_probe(struct platform_device *pdev) phy->div_clk = ERR_PTR(-ENODEV); } - control_node = of_parse_phandle(node, "ctrl-module", 0); - if (!control_node) { - dev_err(&pdev->dev, "Failed to get control device phandle\n"); - return -EINVAL; - } - - control_pdev = of_find_device_by_node(control_node); - if (!control_pdev) { - dev_err(&pdev->dev, "Failed to get control device\n"); - return -EINVAL; - } - - phy->control_dev = &control_pdev->dev; - omap_control_phy_power(phy->control_dev, 0); platform_set_drvdata(pdev, phy);