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Thu, 08 May 2014 14:56:12 +0900 (KST) From: "Arjun.K.V" To: linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: mm: Add workaround for erratum 763126 Date: Thu, 08 May 2014 11:25:08 +0530 Message-id: <1399528508-2806-1-git-send-email-arjun.kv@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsWyRsSkVrdGJjvYYE2XpcXylbtYLN4v62G0 WLB9JZPF/84T7BabHl9jtbh9mddi3fFNzA7sHmvmrWH0aGnuYfPYOesuu8eCTaUem5fUe/Rt WcUYwBbFZZOSmpNZllqkb5fAlbGh4wB7wQ/5ilXLl7M1MM6S7GLk5JAQMJFY3HScBcIWk7hw bz1bFyMXh5DAUkaJr+svMcIUrdy7kgUiMZ1R4szqv2AdQgITmCQm9UiB2GwCGhIb/7Yyg9gi Ag4Sy64eBqthFqiW+NXeA2YLC1hLTNg6E6iGg4NFQFXi0Z06kDCvgLPE++4uRpCwhICCxJxJ NiCrJATa2SWevZsPNpJFQEDi2+RDLBA1shKbDjBDnCYpcXDFDZYJjIILGBlWMYqmFiQXFCel FxnrFSfmFpfmpesl5+duYgQG7ul/z/p3MN49YH2IMRlo3ERmKdHkfGDg55XEGxqbGVmYmpga G5lbmpEmrCTOe/9hUpCQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxtrs311smVy5/03yV1fP Lw9TzmW7vqFh9TEPtidvLysuWGbCF73A/hqDtuPMLoG02wH3SmLfeDzc4ndVye7pnwvuBpba PqeOe3XUKnz3VFvQcG9qwPYtG40+7JZ7JNEcf6Zk34a5H+5wVE4wf/m7bvHb+446S15xNvrv OLpBxHHx4Yfdk7jdvJVYijMSDbWYi4oTAV0VKARyAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDIsWRmVeSWpSXmKPExsVy+t9jQd0amexgg6uz9CyWr9zFYvF+WQ+j xYLtK5ks/neeYLfY9Pgaq8Xty7wW645vYnZg91gzbw2jR0tzD5vHzll32T0WbCr12Lyk3qNv yyrGALaoBkabjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfM HKBTlBTKEnNKgUIBicXFSvp2mCaEhrjpWsA0Ruj6hgTB9RgZoIGENYwZGzoOsBf8kK9YtXw5 WwPjLMkuRk4OCQETiZV7V7JA2GISF+6tZ+ti5OIQEpjOKHFm9V+whJDABCaJST1SIDabgIbE xr+tzCC2iICDxLKrh8FqmAWqJX6194DZwgLWEhO2zgSq4eBgEVCVeHSnDiTMK+As8b67ixEk LCGgIDFnks0ERu4FjAyrGEVTC5ILipPScw31ihNzi0vz0vWS83M3MYLj4pnUDsaVDRaHGAU4 GJV4eDOcs4KFWBPLiitzDzFKcDArifDG8WQHC/GmJFZWpRblxxeV5qQWH2JMBto9kVlKNDkf GLN5JfGGxibmpsamliYWJmaWpAkrifMeaLUOFBJITyxJzU5NLUgtgtnCxMEp1cAoXnif6/HZ G28eqy892GLksXjNlcMe1cz1mcye7PNFpr6o/PTDepGDvlLg7UfxvuXPDBbfmttaICJcNDHF M3jO2938Gxd5Xbi8SI4lu+lnda3ansrQ2hXnpn78sWOVWJop6zuVtzXX34dVBelfWrk/n/FH olzuBJ63h5+d87yxxmXhft1WjjtXlViKMxINtZiLihMBLqWmY88CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140507_225637_264716_FAB15B17 X-CRM114-Status: GOOD ( 13.59 ) X-Spam-Score: -5.7 (-----) Cc: "Arjun.K.V" , catalin.marinas@arm.com, kvarjun@gmail.com, olofj@google.com, dianders@google.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Arjun.K.V" Three processor exclusive access livelock. In a system with three or more coherent masters that all use the ldrex/strex synchronization primitives to access a semaphore in coherent cacheable memory, there is a possibility of a livelock condition where two masters continuously attempt and fail to get the lock while the third master continuously reads the lock. Workaround is to set the "Snoop-delayed exclusive handling" bit in the Auxiliary Control Register, ACTLR[31] to 1. This hardware is installed in each processor to detect that the load/store exclusive livelock scenario may be occurring and delay snoops for a period of time to allow the load exclusive/store exclusive loop to complete and make forward progress. Change-Id: Idcf066e25ea6571a0f5da6f3a770318c1a9d6fff Signed-off-by: Arjun.K.V --- arch/arm/Kconfig | 13 +++++++++++++ arch/arm/mm/proc-v7.S | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index db3c541..80b8562 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1464,6 +1464,19 @@ source "drivers/pci/pcie/Kconfig" source "drivers/pcmcia/Kconfig" +config ARM_ERRATA_763126 + bool "ARM errata: Three processor exclusive access livelock" + depends on CPU_V7 && SMP + help + This enables the workaround got ARM Erratum 763126. + In a system with three or more coherent masters that all use the + ldrex/strex synchronization primitives to access a semaphore in + coherent cacheable memory, there is a possibility of a livelock + condition where two masters continuously attempt and fail to get + the lock while the third master continuously reads the lock. + Workaround is to set the "Snoop-delayed exclusive handling" bit + in the Auxiliary Control Register, ACTLR[31] to 1. + endmenu menu "Kernel Features" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 195731d..e6d22c7 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -136,6 +136,29 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 1 @ TTB 1 #endif mcr p15, 0, r11, c2, c0, 2 @ TTB control register + +#ifdef CONFIG_ARM_ERRATA_763126 + mrc p15, 0, r0, c0, c0, 0 @ Check if we are A15s + ubfx r1, r0, #4, #12 + ldr r2, =0x00000c0f + teq r1, r2 + bne 6f + and r1, r0, #0x00f00000 + and r2, r0, #0x0000000f + orr r2, r2, r1, lsr #20-4 + cmp r2, #0x20 @ Is the revision < r2p0 + blt 6f @ If so, skip + mrc p15, 1, r0, c9, c0, 2 @ read L2 Control register + and r1, r0, #0x03000000 + cmp r1, #0x02000000 @ less than 3 A15 cores? + blt 6f @ if yes, erratum doesnt apply + /* Read and set auxiliary register */ + mrc p15, 0, r0, c1, c0, 1 @ Read Auxiliary control register + orr r0, r0, #(0x1 << 31) @ Set ACTLR[31] bit + mcr p15, 0, r0, c1, c0, 1 @ Write to Auxiliary control register + +6: +#endif ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR mcr p15, 0, r4, c10, c2, 0 @ write PRRR @@ -350,6 +373,26 @@ __v7_setup: mcrle p15, 0, r10, c1, c0, 1 @ write aux control register #endif +#ifdef CONFIG_ARM_ERRATA_763126 + /* + * Add workaround for 763126, by setting the ACTLR[31] = 1. + * This bit enables Snoop-delayed exclusive handling feature, + * which delay snoops for a period of time to allow the + * load exclusive/store exclusive loop to complete + * and make forward progress. + * The resume path setting is taken care in cpu_v7_do_resume + */ + cmp r6, #0x20 @ present from r2p0 onwards + blt 5f + mrc p15, 1, r0, c9, c0, 2 @ read L2 Control register + and r1, r0, #0x03000000 + cmp r1, #0x02000000 @ less than 3 A15 cores? + blt 5f @ if yes, erratum doesnt apply + mrc p15, 0, r5, c1, c0, 1 @ read Auxiliary Control register + orr r5, r5, #(0x1 << 31) + mcr p15, 0, r5, c1, c0, 1 @ set Auxiliary Control register +5: +#endif 4: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate #ifdef CONFIG_MMU