From patchwork Thu May 15 10:40:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 4181441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3AE2FBFF02 for ; Thu, 15 May 2014 10:44:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 55F182037B for ; Thu, 15 May 2014 10:44:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7705620379 for ; Thu, 15 May 2014 10:44:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wkt6v-0003y6-Nh; Thu, 15 May 2014 10:42:01 +0000 Received: from perceval.ideasonboard.com ([95.142.166.194]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wkt6s-0003pH-JE for linux-arm-kernel@lists.infradead.org; Thu, 15 May 2014 10:41:59 +0000 Received: from avalon.ideasonboard.com (135.5-200-80.adsl-dyn.isp.belgacom.be [80.200.5.135]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 17ABB35A3C; Thu, 15 May 2014 12:38:04 +0200 (CEST) From: Laurent Pinchart To: iommu@lists.linux-foundation.org Subject: [PATCH v2 05/10] iommu/ipmmu-vmsa: Set the PTE contiguous hint bit when possible Date: Thu, 15 May 2014 12:40:46 +0200 Message-Id: <1400150451-13469-6-git-send-email-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 1.8.5.5 In-Reply-To: <1400150451-13469-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com> References: <1400150451-13469-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140515_034158_831933_B736D671 X-CRM114-Status: GOOD ( 12.07 ) X-Spam-Score: -0.7 (/) Cc: linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The contiguous hint bit signals to the IOMMU that a range of 16 PTEs refer to physically contiguous memory. It improves performances by dividing the number of TLB lookups by 16, effectively implementing 64kB page sizes. Signed-off-by: Laurent Pinchart --- drivers/iommu/ipmmu-vmsa.c | 43 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index b34a4b7b..150e18e 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -209,6 +209,9 @@ static LIST_HEAD(ipmmu_devices); #define ARM_VMSA_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) #define ARM_VMSA_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) +#define ARM_VMSA_PTE_CONT_ENTRIES 16 +#define ARM_VMSA_PTE_CONT_SIZE (PAGE_SIZE * ARM_VMSA_PTE_CONT_ENTRIES) + #define IPMMU_PTRS_PER_PTE 512 #define IPMMU_PTRS_PER_PMD 512 #define IPMMU_PTRS_PER_PGD 4 @@ -569,10 +572,44 @@ static int ipmmu_alloc_init_pte(struct ipmmu_vmsa_device *mmu, pmd_t *pmd, pteval |= ARM_VMSA_PTE_SH_IS; start = pte; - /* Install the page table entries. */ + /* + * Install the page table entries. + * + * Set the contiguous hint in the PTEs where possible. The hint + * indicates a series of ARM_VMSA_PTE_CONT_ENTRIES PTEs mapping a + * physically contiguous region with the following constraints: + * + * - The region start is aligned to ARM_VMSA_PTE_CONT_SIZE + * - Each PTE in the region has the contiguous hint bit set + * + * We don't support partial unmapping so there's no need to care about + * clearing the contiguous hint from neighbour PTEs. + */ do { - *pte++ = pfn_pte(pfn++, __pgprot(pteval)); - addr += PAGE_SIZE; + unsigned long chunk_end; + + /* + * If the address is aligned to a contiguous region size and the + * mapping size is large enough, process the largest possible + * number of PTEs multiple of ARM_VMSA_PTE_CONT_ENTRIES. + * Otherwise process the smallest number of PTEs to align the + * address to a contiguous region size or to complete the + * mapping. + */ + if (IS_ALIGNED(addr, ARM_VMSA_PTE_CONT_SIZE) && + end - addr >= ARM_VMSA_PTE_CONT_SIZE) { + chunk_end = round_down(end, ARM_VMSA_PTE_CONT_SIZE); + pteval |= ARM_VMSA_PTE_CONT; + } else { + chunk_end = min(ALIGN(addr, ARM_VMSA_PTE_CONT_SIZE), + end); + pteval &= ~ARM_VMSA_PTE_CONT; + } + + do { + *pte++ = pfn_pte(pfn++, __pgprot(pteval)); + addr += PAGE_SIZE; + } while (addr != chunk_end); } while (addr != end); ipmmu_flush_pgtable(mmu, start, sizeof(*pte) * (pte - start));