From patchwork Thu May 15 17:58:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 4184751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 70E70BFF02 for ; Thu, 15 May 2014 18:01:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A89A7202FF for ; Thu, 15 May 2014 18:00:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 976892017D for ; Thu, 15 May 2014 18:00:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WkzvP-0007Po-5u; Thu, 15 May 2014 17:58:35 +0000 Received: from mail-ig0-f170.google.com ([209.85.213.170]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WkzvM-0006zG-9d for linux-arm-kernel@lists.infradead.org; Thu, 15 May 2014 17:58:32 +0000 Received: by mail-ig0-f170.google.com with SMTP id r10so681191igi.3 for ; Thu, 15 May 2014 10:58:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nNrcWUxU0HsL95yM4Dp1lksCS7xHSBXnyxN+QxCAP8g=; b=MAR96SCaGRIQNQYfIeMW45O+u/wlfGFosEEXJi7HmOM9yFY15UWiu4ECKBGskWq2w5 iL7Qs40YjAVFMkFtIKsjuVvtianB2o5DbBKUObgpObe2afNV3zEYjJn7rluCp294GEaN cCCTgd1e7Fj5SWeexTpX1K/6IQixBbEm04LgCYbJxwdQzhAN8EwY9T4TDNYkQUUnJV4p t4GrZcK2h45f8NgEj40iFIuxyZnt0w/l+0GuRV7nSxmHDlrxFtpdh7Ag+3p452ucrtev 3W1X+K50bKQn5hOsk77VOvTusnjUzLbA9oj78vHjri/+ObL5K1cCqScc/1NbnRhhbAJx ADdA== X-Gm-Message-State: ALoCoQm/rHx04p+hQz4FZFRKoyXFbTninJZygZ751y+SqHY5OuP3eFzGgninxu61RatJGE2tVqSw X-Received: by 10.50.22.210 with SMTP id g18mr74888908igf.19.1400176686691; Thu, 15 May 2014 10:58:06 -0700 (PDT) Received: from localhost.localdomain (c-71-195-31-37.hsd1.mn.comcast.net. [71.195.31.37]) by mx.google.com with ESMTPSA id ql7sm47185754igc.19.2014.05.15.10.58.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 May 2014 10:58:06 -0700 (PDT) From: Alex Elder To: mporter@linaro.org, bcm@fixthebug.org, linux@arm.linux.org.uk, devicetree@vger.kernel.org, arnd@arndb.de, sboyd@codeaurora.org Subject: [PATCH v3 RESEND 1/5] devicetree: bindings: document Broadcom CPU enable method Date: Thu, 15 May 2014 12:58:07 -0500 Message-Id: <1400176691-26058-2-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400176691-26058-1-git-send-email-elder@linaro.org> References: <1400176691-26058-1-git-send-email-elder@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140515_105832_374284_0CF1D389 X-CRM114-Status: GOOD ( 10.94 ) X-Spam-Score: -0.7 (/) Cc: bcm-kernel-feedback-list@broadcom.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Broadcom mobile SoCs use a ROM-implemented holding pen for controlled boot of secondary cores. A special register is used to communicate to the ROM that a secondary core should start executing kernel code. This enable method is currently used for members of the bcm281xx and bcm21664 SoC families. The use of an enable method also allows the SMP operation vector to be assigned as a result of device tree content for these SoCs. Signed-off-by: Alex Elder --- Documentation/devicetree/bindings/arm/cpus.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 333f4ae..c6a2411 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -185,6 +185,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "brcm,bcm11351-cpu-method" - cpu-release-addr Usage: required for systems that have an "enable-method" @@ -209,6 +210,17 @@ nodes to be present and contain the properties described below. Value type: Definition: Specifies the ACC[2] node associated with this CPU. + - secondary-boot-reg + Usage: + Required for systems that have an "enable-method" + property value of "brcm,bcm11351-cpu-method". + Value type: + Definition: + Specifies the physical address of the register used to + request the ROM holding pen code release a secondary + CPU. The value written to the register is formed by + encoding the target CPU id into the low bits of the + physical start address it should jump to. Example 1 (dual-cluster big.LITTLE system 32-bit):