From patchwork Fri May 16 08:49:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Longchamp X-Patchwork-Id: 4189391 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DA16DBFF02 for ; Fri, 16 May 2014 08:52:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E957F202EA for ; Fri, 16 May 2014 08:52:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B074D20272 for ; Fri, 16 May 2014 08:52:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WlDq3-0003EM-PO; Fri, 16 May 2014 08:49:59 +0000 Received: from mail-de.keymile.com ([195.8.104.250]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WlDpi-00035t-KU for linux-arm-kernel@lists.infradead.org; Fri, 16 May 2014 08:49:40 +0000 Received: from frodo.de.keymile.net ([10.9.1.54]:48231 helo=mailrelay.de.keymile.net) by mail-de.keymile.com with esmtp (Exim 4.76) (envelope-from ) id 1WlDpI-0003tu-3B; Fri, 16 May 2014 10:49:13 +0200 Received: from ch900166.keymile.net (ch900166.keymile.net [172.31.40.218]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id s4G8n4Lg002438; Fri, 16 May 2014 10:49:11 +0200 (MEST) From: Valentin Longchamp To: Linux ARM Kernel , Jason Cooper , Andrew Lunn Subject: [PATCH v2 1/3] ARM: dts: kirkwood: resynch 98dx4122 dtsi Date: Fri, 16 May 2014 10:49:01 +0200 Message-Id: <1400230143-15620-2-git-send-email-valentin.longchamp@keymile.com> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1400230143-15620-1-git-send-email-valentin.longchamp@keymile.com> References: <1400230143-15620-1-git-send-email-valentin.longchamp@keymile.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140516_014938_896731_01D8C835 X-CRM114-Status: UNSURE ( 9.61 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: Linux device trees , Valentin Longchamp X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The 98DX4122 dtsi file lacks the defintion of the PCIe controller which is present on this SoC. The SATA phys must also be explicitely disabled since they are not present on this SoC. If they remain enabled, a hardlock occures when their clock gates are enabled. Signed-off-by: Valentin Longchamp Acked-by: Sebastian Hesselbarth --- Changes in v2: None arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 43 ++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 2e8e412..9e1f741 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -1,4 +1,39 @@ / { + mbus { + pciec: pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + }; + ocp@f1000000 { pinctrl: pin-controller@10000 { compatible = "marvell,98dx4122-pinctrl"; @@ -6,3 +41,11 @@ }; }; }; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +};