From patchwork Tue May 20 21:09:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 4213011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 78F229F32A for ; Tue, 20 May 2014 21:13:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 814A52035E for ; Tue, 20 May 2014 21:13:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 803A32035D for ; Tue, 20 May 2014 21:13:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmrJ9-0004QX-Ll; Tue, 20 May 2014 21:10:47 +0000 Received: from mail-oa0-x233.google.com ([2607:f8b0:4003:c02::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmrIf-0003Dp-4s for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 21:10:18 +0000 Received: by mail-oa0-f51.google.com with SMTP id n16so1218442oag.24 for ; Tue, 20 May 2014 14:10:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cWkCbUDYBMrgq6NT7E/BjDz8yjJf8kW3C2t+V29bGxs=; b=QsB1iNhEyIZ6cgi8LXOkYdBEUvNrA7jWwX0YVrddZRwh2UDkLFzX2AiK47gqENF36z yD1ozWEDgChp8vFXJKRg0NTy0pYVw8VKK2tjSxcAj5ZdJqILzCvEP880FJTKb6mieDvi 9WYaedrGhXd+OOG2AXZ2PxljRLVkSvLUOGvOjG7farAzCFvUzO1BUQ6Z5ETiQwOeeISf Zvf/opBS6uPy2fl4ExknUg0ZrNunYe6OBiwHubHEuPIzk0a61x460lsg2U48w9/xfaks mIYQfyUkpLEQLpIL2fyQB9RZRuXRzsMXC0Lp0/vA4uxIXXaJsEBCESTh4rzVjCZcb8Pd wvSg== X-Received: by 10.60.131.40 with SMTP id oj8mr46249366oeb.14.1400620200696; Tue, 20 May 2014 14:10:00 -0700 (PDT) Received: from localhost.localdomain (66-90-144-10.dyn.grandenetworks.net. [66.90.144.10]) by mx.google.com with ESMTPSA id qp6sm39817593obb.14.2014.05.20.14.09.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 May 2014 14:10:00 -0700 (PDT) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 09/10] dts: versatile: add clock tree Date: Tue, 20 May 2014 16:09:35 -0500 Message-Id: <1400620176-7239-10-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400620176-7239-1-git-send-email-robherring2@gmail.com> References: <1400620176-7239-1-git-send-email-robherring2@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_141017_318413_28B3C8F1 X-CRM114-Status: GOOD ( 10.60 ) X-Spam-Score: 0.1 (/) Cc: Rob Herring , linus.walleij@linaro.org, arm@kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Herring The versatile dts is missing any clock data. Add the clocks. It is not clear from the documentation where pclk comes from, so for now it is a dummy clock which is sufficient for things to work. Signed-off-by: Rob Herring --- arch/arm/boot/dts/versatile-ab.dts | 74 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/versatile-pb.dts | 10 ++++++ 2 files changed, 84 insertions(+) diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index e4cba63..37e01b4 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -19,6 +19,40 @@ reg = <0x0 0x08000000>; }; + core-module@10000000 { + compatible = "arm,core-module-versatile"; + reg = <0x10000000 0x200>; + + osc24M: oscillator@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + /* OSC1 on AB, OSC4 on PB */ + osc1: cm_aux_osc@24M { + #clock-cells = <0>; + compatible = "arm,versatile-cm-auxosc"; + clocks = <&osc24M>; + }; + + /* The timer clock is the 24 MHz oscillator divided to 1MHz */ + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&osc24M>; + }; + + /* Actually hclk ? */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + flash@34000000 { compatible = "arm,versatile-flash"; reg = <0x34000000 0x4000000>; @@ -79,63 +113,85 @@ compatible = "arm,pl081", "arm,primecell"; reg = <0x10130000 0x1000>; interrupts = <17>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; uart0: uart@101f1000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f1000 0x1000>; interrupts = <12>; + clocks = <&osc24M>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; uart1: uart@101f2000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f2000 0x1000>; interrupts = <13>; + clocks = <&osc24M>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; uart2: uart@101f3000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f3000 0x1000>; interrupts = <14>; + clocks = <&osc24M>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; smc@10100000 { compatible = "arm,primecell"; reg = <0x10100000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; mpmc@10110000 { compatible = "arm,primecell"; reg = <0x10110000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; display@10120000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x10120000 0x1000>; interrupts = <16>; + clocks = <&osc1>, <&pclk>; + clock-names = "clcd", "apb_pclk"; }; sctl@101e0000 { compatible = "arm,primecell"; reg = <0x101e0000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; watchdog@101e1000 { compatible = "arm,primecell"; reg = <0x101e1000 0x1000>; interrupts = <0>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; timer@101e2000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x101e2000 0x1000>; interrupts = <4>; + clocks = <&timclk>, <&pclk>; + clock-names = "tmrclk", "apb_pclk"; }; timer@101e3000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x101e3000 0x1000>; interrupts = <5>; + clocks = <&timclk>, <&pclk>; + clock-names = "tmrclk", "apb_pclk"; }; gpio0: gpio@101e4000 { @@ -146,6 +202,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; gpio1: gpio@101e5000 { @@ -156,24 +214,32 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; rtc@101e8000 { compatible = "arm,pl030", "arm,primecell"; reg = <0x101e8000 0x1000>; interrupts = <10>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; sci@101f0000 { compatible = "arm,primecell"; reg = <0x101f0000 0x1000>; interrupts = <15>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; ssp@101f4000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x101f4000 0x1000>; interrupts = <11>; + clocks = <&osc24M>, <&pclk>; + clock-names = "sspclk", "apb_pclk"; }; fpga { @@ -186,23 +252,31 @@ compatible = "arm,primecell"; reg = <0x4000 0x1000>; interrupts = <24>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; mmc@5000 { compatible = "arm,pl180", "arm,primecell"; reg = < 0x5000 0x1000>; interrupts-extended = <&vic 22 &sic 2>; + clocks = <&osc24M>, <&pclk>; + clock-names = "mclk", "apb_pclk"; }; kmi@6000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x6000 0x1000>; interrupt-parent = <&sic>; interrupts = <3>; + clocks = <&osc24M>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; kmi@7000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x7000 0x1000>; interrupt-parent = <&sic>; interrupts = <4>; + clocks = <&osc24M>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; }; }; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index a428541..473081d 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -13,6 +13,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; gpio3: gpio@101e7000 { @@ -23,6 +25,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; fpga { @@ -31,17 +35,23 @@ reg = <0x9000 0x1000>; interrupt-parent = <&sic>; interrupts = <6>; + clocks = <&osc24M>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; sci@a000 { compatible = "arm,primecell"; reg = <0xa000 0x1000>; interrupt-parent = <&sic>; interrupts = <5>; + clocks = <&osc24M>; + clock-names = "apb_pclk"; }; mmc@b000 { compatible = "arm,pl180", "arm,primecell"; reg = <0xb000 0x1000>; interrupts-extended = <&vic 23 &sic 2>; + clocks = <&osc24M>, <&pclk>; + clock-names = "mclk", "apb_pclk"; }; }; };