From patchwork Thu May 22 15:20:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 4223881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 364D5BF90B for ; Thu, 22 May 2014 15:25:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 84D4E2037A for ; Thu, 22 May 2014 15:25:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E39C220379 for ; Thu, 22 May 2014 15:25:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WnUoZ-0001c7-Ej; Thu, 22 May 2014 15:21:51 +0000 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WnUoU-0001DG-4U for linux-arm-kernel@lists.infradead.org; Thu, 22 May 2014 15:21:46 +0000 Received: from wens by mirror2.csie.ntu.edu.tw with local (Exim 4.82) (envelope-from ) id 1WnUo0-00010j-QZ; Thu, 22 May 2014 23:21:16 +0800 From: Chen-Yu Tsai To: Maxime Ripard , Linus Walleij Subject: [PATCH] pinctrl: sunxi: fix pin numbers passed to register offset helpers Date: Thu, 22 May 2014 23:20:55 +0800 Message-Id: <1400772055-3852-1-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.0.0.rc2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140522_082146_339135_0DA071AF X-CRM114-Status: GOOD ( 11.28 ) X-Spam-Score: -0.7 (/) Cc: Boris BREZILLON , Chen-Yu Tsai , linux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses. This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers. Signed-off-by: Chen-Yu Tsai Reviewed-by: Boris Brezillon --- Hi, This patch fixes the pinctrl driver failing to set pinmuxes for the R_PIO block found on the A31 and A23. The problem was found while working on bringing up the A23 SoC. The R_UART pins weren't properly muxed when the bootloader didn't use them. A thank you to Boris who also verified the issue. Cheers, ChenYu --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index f6522b5..59962fa 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -280,6 +280,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sunxi_pinctrl_group *g = &pctl->groups[group]; unsigned long flags; + unsigned pin = g->pin - pctl->desc->pin_base; u32 val, mask; u16 strength; u8 dlevel; @@ -303,23 +304,23 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, * 3: 40mA */ dlevel = strength / 10 - 1; - val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); - mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); + val = readl(pctl->membase + sunxi_dlevel_reg(pin)); + mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); writel((val & ~mask) - | dlevel << sunxi_dlevel_offset(g->pin), - pctl->membase + sunxi_dlevel_reg(g->pin)); + | dlevel << sunxi_dlevel_offset(pin), + pctl->membase + sunxi_dlevel_reg(pin)); break; case PIN_CONFIG_BIAS_PULL_UP: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); + val = readl(pctl->membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(pin); + writel((val & ~mask) | 1 << sunxi_pull_offset(pin), + pctl->membase + sunxi_pull_reg(pin)); break; case PIN_CONFIG_BIAS_PULL_DOWN: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); + val = readl(pctl->membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(pin); + writel((val & ~mask) | 2 << sunxi_pull_offset(pin), + pctl->membase + sunxi_pull_reg(pin)); break; default: break; @@ -376,6 +377,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pctl->lock, flags); + pin -= pctl->desc->pin_base; val = readl(pctl->membase + sunxi_mux_reg(pin)); mask = MUX_PINS_MASK << sunxi_mux_offset(pin); writel((val & ~mask) | config << sunxi_mux_offset(pin),