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[01/22] serial: 8250_dw: Add optional reset control support

Message ID 1400831485-28576-2-git-send-email-wens@csie.org
State New, archived
Headers show

Commit Message

Chen-Yu Tsai May 23, 2014, 7:51 a.m. UTC
The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.

This patch adds optional reset support to the driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt |  1 +
 drivers/tty/serial/8250/8250_dw.c                             | 10 ++++++++++
 2 files changed, 11 insertions(+)

Comments

Arnd Bergmann May 23, 2014, 8:19 a.m. UTC | #1
On Friday 23 May 2014 15:51:04 Chen-Yu Tsai wrote:
>                 p->regshift = val;
>  
> +       data->rst = devm_reset_control_get_optional(p->dev, NULL);
> +
>         /* clock got configured through clk api, all done */
>         if (p->uartclk)
>                 return 0;
> @@ -362,6 +366,9 @@ static int dw8250_probe(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>  
> +       if (!IS_ERR_OR_NULL(data->rst))
> +               reset_control_deassert(data->rst);
> +

You should basically never use IS_ERR_OR_NULL(). devm_reset_control_get_optional()
doesn't return NULL, so IS_ERR() should be safe.

Alternatively, change the code above to set data->rst to NULL if there
is no reset line or error out if you get a different error (e.g. EPROBE_DEFER).

	Arnd
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index f13f1c5..cb9af84 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
@@ -7,6 +7,7 @@  Required properties:
 - clock-frequency : the input clock frequency for the UART.
 
 Optional properties:
+- resets : phandle to the parent reset controller.
 - reg-shift : quantity to shift the register offsets by.  If this property is
   not present then the register offsets are not shifted.
 - reg-io-width : the size (in bytes) of the IO accesses that should be
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index ed31135..d0c6d080 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -26,6 +26,7 @@ 
 #include <linux/slab.h>
 #include <linux/acpi.h>
 #include <linux/clk.h>
+#include <linux/reset.h>
 #include <linux/pm_runtime.h>
 
 #include <asm/byteorder.h>
@@ -59,6 +60,7 @@  struct dw8250_data {
 	int			last_mcr;
 	int			line;
 	struct clk		*clk;
+	struct reset_control	*rst;
 	struct uart_8250_dma	dma;
 };
 
@@ -259,6 +261,8 @@  static int dw8250_probe_of(struct uart_port *p,
 	if (!of_property_read_u32(np, "reg-shift", &val))
 		p->regshift = val;
 
+	data->rst = devm_reset_control_get_optional(p->dev, NULL);
+
 	/* clock got configured through clk api, all done */
 	if (p->uartclk)
 		return 0;
@@ -362,6 +366,9 @@  static int dw8250_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	if (!IS_ERR_OR_NULL(data->rst))
+		reset_control_deassert(data->rst);
+
 	data->line = serial8250_register_8250_port(&uart);
 	if (data->line < 0)
 		return data->line;
@@ -382,6 +389,9 @@  static int dw8250_remove(struct platform_device *pdev)
 
 	serial8250_unregister_port(data->line);
 
+	if (!IS_ERR_OR_NULL(data->rst))
+		reset_control_assert(data->rst);
+
 	if (!IS_ERR(data->clk))
 		clk_disable_unprepare(data->clk);