From patchwork Sat May 31 06:01:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 4274941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 26F89BEECB for ; Sat, 31 May 2014 06:05:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 388EE203AC for ; Sat, 31 May 2014 06:05:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DB4920397 for ; Sat, 31 May 2014 06:05:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WqcNJ-0007gr-Un; Sat, 31 May 2014 06:02:37 +0000 Received: from smtp29.i.mail.ru ([94.100.177.89]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WqcMt-0007cT-MS for linux-arm-kernel@lists.infradead.org; Sat, 31 May 2014 06:02:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=4Lu5XWvxg64NPxP/i+W8+4kD/ZaPKCasMb/MESxFF9w=; b=j+KAfmELHMhEVksBqKwk9p5k/5o8uJMmjPhvYYnrxrp4PTEFdw4Y2BirppT7tUVIjfrbYK2cATCA5dNrig0yXlIrb/99I9aSsOHBnXDNvBd+HGM6IL0hvBFuIlVhUHzyvu2whqsmj87KO/Iwm+XG7ejVWMNIUjyRVD0T5BshDTg=; Received: from [5.18.98.7] (port=52298 helo=shc.zet) by smtp29.i.mail.ru with esmtpa (envelope-from ) id 1WqcMU-0007V2-MD; Sat, 31 May 2014 10:01:46 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] ARM: i.MX: tzic: Use irqchip_init() for IRQ initialization in DT case Date: Sat, 31 May 2014 10:01:31 +0400 Message-Id: <1401516095-31020-2-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.8.5.5 In-Reply-To: <1401516095-31020-1-git-send-email-shc_work@mail.ru> References: <1401516095-31020-1-git-send-email-shc_work@mail.ru> X-Mras: Ok X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140530_230212_344014_D81B3051 X-CRM114-Status: GOOD ( 16.13 ) X-Spam-Score: -0.1 (/) Cc: Alexander Shiyan , Sascha Hauer , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use generic irqchip_init() DT call to initialize IRQs, so after this patch, the mxc-tzic driver is quite prepared to move to drivers/irqchip. As a temporary solution to do it, we use OF_DECLARE_2() instead of IRQCHIP_DECLARE(). Signed-off-by: Alexander Shiyan --- arch/arm/mach-imx/common.h | 1 - arch/arm/mach-imx/mach-imx50.c | 1 - arch/arm/mach-imx/mach-imx51.c | 1 - arch/arm/mach-imx/mach-imx53.c | 1 - arch/arm/mach-imx/tzic.c | 19 +++++++++++-------- 5 files changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 5aaea2b..9586187 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -33,7 +33,6 @@ void imx27_init_early(void); void imx31_init_early(void); void imx35_init_early(void); void mxc_init_irq(void __iomem *); -void tzic_init_irq(void); void mx1_init_irq(void); void mx21_init_irq(void); void mx25_init_irq(void); diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c index 62a4d45..f8d0030 100644 --- a/arch/arm/mach-imx/mach-imx50.c +++ b/arch/arm/mach-imx/mach-imx50.c @@ -29,7 +29,6 @@ static const char *imx50_dt_board_compat[] __initconst = { }; DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") - .init_irq = tzic_init_irq, .init_machine = imx50_dt_init, .dt_compat = imx50_dt_board_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c index b6f42f8..bd4e9eb 100644 --- a/arch/arm/mach-imx/mach-imx51.c +++ b/arch/arm/mach-imx/mach-imx51.c @@ -74,7 +74,6 @@ static const char *imx51_dt_board_compat[] __initconst = { DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") .init_early = imx51_init_early, - .init_irq = tzic_init_irq, .init_machine = imx51_dt_init, .init_late = imx51_init_late, .dt_compat = imx51_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index d8c3c08..37650b0 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -48,7 +48,6 @@ static const char *imx53_dt_board_compat[] __initconst = { DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") .init_early = imx53_init_early, - .init_irq = tzic_init_irq, .init_machine = imx53_dt_init, .init_late = imx53_init_late, .dt_compat = imx53_dt_board_compat, diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c index 1d4f384..b5fc0c7 100644 --- a/arch/arm/mach-imx/tzic.c +++ b/arch/arm/mach-imx/tzic.c @@ -109,7 +109,7 @@ static __init void tzic_init_gc(int idx, unsigned int irq_start) struct irq_chip_generic *gc; struct irq_chip_type *ct; - gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, + gc = irq_alloc_generic_chip("mxc-tzic", 1, irq_start, tzic_base, handle_level_irq); gc->private = &tzic_extra_irq; gc->wake_enabled = IRQ_MSK(32); @@ -154,15 +154,15 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ -void __init tzic_init_irq(void) +static int __init tzic_init_irq(struct device_node *np, + struct device_node *parent) { - struct device_node *np; int irq_base; int i; - np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); tzic_base = of_iomap(np, 0); - WARN_ON(!tzic_base); + if (!tzic_base) + return -ENOMEM; /* put the TZIC into the reset value with * all interrupts disabled @@ -183,11 +183,13 @@ void __init tzic_init_irq(void) /* all IRQ no FIQ Warning :: No selection */ irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); - WARN_ON(irq_base < 0); + if (irq_base < 0) + return -ENOMEM; domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, &irq_domain_simple_ops, NULL); - WARN_ON(!domain); + if (!domain) + return -ENOMEM; for (i = 0; i < 4; i++, irq_base += 32) tzic_init_gc(i, irq_base); @@ -199,8 +201,9 @@ void __init tzic_init_irq(void) init_FIQ(FIQ_START); #endif - pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); + return 0; } +OF_DECLARE_2(irqchip, mxc_tzic, "fsl,tzic", tzic_init_irq); /** * tzic_enable_wake() - enable wakeup interrupt