From patchwork Sat Jun 21 14:22:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 4394161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 44CAC9F314 for ; Sat, 21 Jun 2014 14:26:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4023B2024D for ; Sat, 21 Jun 2014 14:26:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C26F2024C for ; Sat, 21 Jun 2014 14:26:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WyMDG-0001Am-89; Sat, 21 Jun 2014 14:24:14 +0000 Received: from mail-wi0-x234.google.com ([2a00:1450:400c:c05::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WyMD7-0000zU-Na for linux-arm-kernel@lists.infradead.org; Sat, 21 Jun 2014 14:24:07 +0000 Received: by mail-wi0-f180.google.com with SMTP id hi2so2087607wib.7 for ; Sat, 21 Jun 2014 07:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b8ilxeoo2jUQzA77i3mbVkBnwf3PROwux622THL707Q=; b=XstU/FFPG0l8fd45hxztX73QIykNZ2NP1IbPP/eghz4QlH4EK6pQLMmpU7Mlt/eJKl xyzG+EoUG0960TDqAQaVP1m9yiV8+HjOzenWfXXAoR3+HWuQd8z4SuevWKbav6gtta4f PYWcGTjDPnQ/my3tD6Ikl9O0a3qEmNAt2Zef7bu1xvC17FMnHMV3SvK3YQXnDfwBwEX6 /tNzu+NB+SBTuO1LtLTILuGeS5sh/f8Lqkvj412Ec4WhJDtOIg6XPgVGLDGh0Gd6qkOn KD50f2hzS+we/+R6s8m1+B7HGN30q2Uqwsf581l7ypGeoow7W3YHa9rsvQsROpFv1zQb XfSg== X-Received: by 10.194.120.103 with SMTP id lb7mr11991162wjb.40.1403360623034; Sat, 21 Jun 2014 07:23:43 -0700 (PDT) Received: from sark.local (host188-27-dynamic.31-79-r.retail.telecomitalia.it. [79.31.27.188]) by mx.google.com with ESMTPSA id rw4sm22667978wjb.44.2014.06.21.07.23.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Jun 2014 07:23:42 -0700 (PDT) From: Beniamino Galvani To: Thierry Reding Subject: [PATCH v2 1/3] pwm: add Rockchip SoC PWM support Date: Sat, 21 Jun 2014 16:22:06 +0200 Message-Id: <1403360528-12757-2-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1403360528-12757-1-git-send-email-b.galvani@gmail.com> References: <1403360528-12757-1-git-send-email-b.galvani@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140621_072406_072820_8D038AC2 X-CRM114-Status: GOOD ( 18.94 ) X-Spam-Score: -0.8 (/) Cc: Mark Rutland , linux-pwm@vger.kernel.org, Heiko Stuebner , Pawel Moll , Ian Campbell , Randy Dunlap , linux-kernel@vger.kernel.org, Beniamino Galvani , devicetree@vger.kernel.org, Rob Herring , Kumar Gala , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds a driver for the PWM controller found on Rockchip RK29, RK30 and RK31 SoCs. Signed-off-by: Beniamino Galvani --- drivers/pwm/Kconfig | 7 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rockchip.c | 177 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/pwm/pwm-rockchip.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4ad7b89..a86879a 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -206,6 +206,13 @@ config PWM_RENESAS_TPU To compile this driver as a module, choose M here: the module will be called pwm-renesas-tpu. +config PWM_ROCKCHIP + tristate "Rockchip PWM support" + depends on ARCH_ROCKCHIP + help + Generic PWM framework driver for the PWM controller found on + Rockchip SoCs. + config PWM_SAMSUNG tristate "Samsung PWM support" depends on PLAT_SAMSUNG diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5c86a19..e03e2ae 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o +obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c new file mode 100644 index 0000000..eec2145 --- /dev/null +++ b/drivers/pwm/pwm-rockchip.c @@ -0,0 +1,177 @@ +/* + * PWM driver for Rockchip SoCs + * + * Copyright (C) 2014 Beniamino Galvani + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CNTR 0x00 /* Counter register */ +#define PWM_HRC 0x04 /* High reference register */ +#define PWM_LRC 0x08 /* Low reference register */ +#define PWM_CTRL 0x0c /* Control register */ +#define PWM_CTRL_TIMER_EN (1 << 0) +#define PWM_CTRL_OUTPUT_EN (1 << 3) + +#define PRESCALER 2 + +struct rockchip_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; +}; + +static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) +{ + return container_of(c, struct rockchip_pwm_chip, chip); +} + +static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + unsigned long period, duty; + u64 clk_rate, div; + int ret; + + clk_rate = clk_get_rate(pc->clk); + + /* + * Since period and duty cycle registers have a width of 32 + * bits, every possible input period can be obtained using the + * default prescaler value for all practical clock rate values. + */ + div = clk_rate * period_ns; + do_div(div, PRESCALER * NSEC_PER_SEC); + period = div; + + div = clk_rate * duty_ns; + do_div(div, PRESCALER * NSEC_PER_SEC); + duty = div; + + ret = clk_enable(pc->clk); + if (ret) + return ret; + + writel(period, pc->base + PWM_LRC); + writel(duty, pc->base + PWM_HRC); + writel(0, pc->base + PWM_CNTR); + + clk_disable(pc->clk); + + return 0; +} + +static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + int ret; + u32 val; + + ret = clk_enable(pc->clk); + if (ret) + return ret; + + val = readl_relaxed(pc->base + PWM_CTRL); + val |= PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; + writel_relaxed(val, pc->base + PWM_CTRL); + + return 0; +} + +static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 val; + + val = readl_relaxed(pc->base + PWM_CTRL); + val &= ~(PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN); + writel_relaxed(val, pc->base + PWM_CTRL); + + clk_disable(pc->clk); +} + +static const struct pwm_ops rockchip_pwm_ops = { + .config = rockchip_pwm_config, + .enable = rockchip_pwm_enable, + .disable = rockchip_pwm_disable, + .owner = THIS_MODULE, +}; + +static int rockchip_pwm_probe(struct platform_device *pdev) +{ + struct rockchip_pwm_chip *pc; + struct resource *r; + int ret; + + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pc->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pc->base)) + return PTR_ERR(pc->base); + + pc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pc->clk)) + return PTR_ERR(pc->clk); + + ret = clk_prepare(pc->clk); + if (ret) + return ret; + + platform_set_drvdata(pdev, pc); + + pc->chip.dev = &pdev->dev; + pc->chip.ops = &rockchip_pwm_ops; + pc->chip.base = -1; + pc->chip.npwm = 1; + + ret = pwmchip_add(&pc->chip); + if (ret < 0) { + clk_unprepare(pc->clk); + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); + } + + return ret; +} + +static int rockchip_pwm_remove(struct platform_device *pdev) +{ + struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); + + clk_unprepare(pc->clk); + + return pwmchip_remove(&pc->chip); +} + +static const struct of_device_id rockchip_pwm_dt_ids[] = { + { .compatible = "rockchip,rk2928-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); + +static struct platform_driver rockchip_pwm_driver = { + .driver = { + .name = "rockchip-pwm", + .of_match_table = rockchip_pwm_dt_ids, + }, + .probe = rockchip_pwm_probe, + .remove = rockchip_pwm_remove, +}; +module_platform_driver(rockchip_pwm_driver); + +MODULE_AUTHOR("Beniamino Galvani "); +MODULE_DESCRIPTION("Rockchip SoC PWM driver"); +MODULE_LICENSE("GPL v2");