From patchwork Fri Jun 27 16:58:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 4436621 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5D3C1BEEAA for ; Fri, 27 Jun 2014 17:01:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 65133203AD for ; Fri, 27 Jun 2014 17:01:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7DA132039D for ; Fri, 27 Jun 2014 17:01:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X0ZV7-0004YY-6N; Fri, 27 Jun 2014 16:59:49 +0000 Received: from mail-wi0-x230.google.com ([2a00:1450:400c:c05::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X0ZUc-0004HL-8W for linux-arm-kernel@lists.infradead.org; Fri, 27 Jun 2014 16:59:20 +0000 Received: by mail-wi0-f176.google.com with SMTP id n3so3185883wiv.9 for ; Fri, 27 Jun 2014 09:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Shrj/bIQ/RC6vBNwGVH/HkAhsQZrbxSwl+NS6O+JRK4=; b=0Uj8AwFIIZMdjh17KG2zOMn6SVkBrpjGH5ZPL1yPaaxldGNKaTOIm5a+PNautamOx0 vcAQ7l/xvJK7XcRsxv3YFGp1Zmtr4tusIui5y6EkaHPd9AIDmuyQ9Shxntq7+/E3J0+p car52BZkwiA+UpoYapoQ5kwMX0Z+oGQRzT/CpdsfCgOe17rPRNeFOTasCHb99Toseq4i MlEZHOzdYfMXaD3Rgv0gb+Xv/+CUN3sRKyLf6SLhtuxLtXsxrBfUkdCc7wdhg5z54rps SwdF0BTtKYR5w2szBgIyqPIUdgaFX0Pi3zY43AbFkCofTFx8LXlPXedvJBD3jM8/YsPO fwhQ== X-Received: by 10.180.10.138 with SMTP id i10mr12682416wib.81.1403888334224; Fri, 27 Jun 2014 09:58:54 -0700 (PDT) Received: from localhost (port-35906.pppoe.wtnet.de. [46.59.191.32]) by mx.google.com with ESMTPSA id hc4sm22494067wjc.38.2014.06.27.09.58.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jun 2014 09:58:53 -0700 (PDT) From: Thierry Reding To: Stephen Warren Subject: [RFC 3/4] soc/tegra: Initialize interrupt controller from DT Date: Fri, 27 Jun 2014 18:58:48 +0200 Message-Id: <1403888329-24755-3-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1403888329-24755-1-git-send-email-thierry.reding@gmail.com> References: <1403888329-24755-1-git-send-email-thierry.reding@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140627_095918_663289_59164995 X-CRM114-Status: GOOD ( 17.35 ) X-Spam-Score: -0.8 (/) Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Obtains the register ranges for the legacy interrupt controller from DT and provide hard-coded values as fallback. Signed-off-by: Thierry Reding --- drivers/soc/tegra/iomap.h | 18 ------------ drivers/soc/tegra/irq.c | 75 ++++++++++++++++++++++++++++++++++++----------- 2 files changed, 58 insertions(+), 35 deletions(-) diff --git a/drivers/soc/tegra/iomap.h b/drivers/soc/tegra/iomap.h index ee79808e93a3..52bbb5c8fe84 100644 --- a/drivers/soc/tegra/iomap.h +++ b/drivers/soc/tegra/iomap.h @@ -28,24 +28,6 @@ #define TEGRA_ARM_PERIF_BASE 0x50040000 #define TEGRA_ARM_PERIF_SIZE SZ_8K -#define TEGRA_ARM_INT_DIST_BASE 0x50041000 -#define TEGRA_ARM_INT_DIST_SIZE SZ_4K - -#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 -#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 - -#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 -#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64 - -#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 -#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64 - -#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 -#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 - -#define TEGRA_QUINARY_ICTLR_BASE 0x60004400 -#define TEGRA_QUINARY_ICTLR_SIZE SZ_64 - #define TEGRA_TMR1_BASE 0x60005000 #define TEGRA_TMR1_SIZE SZ_8 diff --git a/drivers/soc/tegra/irq.c b/drivers/soc/tegra/irq.c index 57807a79f5fd..6e04140986b7 100644 --- a/drivers/soc/tegra/irq.c +++ b/drivers/soc/tegra/irq.c @@ -27,8 +27,6 @@ #include #include -#include "iomap.h" - #define ICTLR_CPU_IEP_VFIQ 0x08 #define ICTLR_CPU_IEP_FIR 0x14 #define ICTLR_CPU_IEP_FIR_SET 0x18 @@ -51,13 +49,7 @@ static int num_ictlrs; -static void __iomem *ictlr_reg_base[] = { - IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), -}; +static void __iomem *ictlr_reg_base[] = { NULL, NULL, NULL, NULL, NULL }; #ifdef CONFIG_PM_SLEEP static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; @@ -69,10 +61,11 @@ static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; static void __iomem *tegra_gic_cpu_base; #endif +static void __iomem *distbase; + bool tegra_pending_sgi(void) { u32 pending_set; - void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET); @@ -254,24 +247,71 @@ static void tegra114_gic_cpu_pm_registration(void) static void tegra114_gic_cpu_pm_registration(void) { } #endif +static struct resource ictlr_regs[] = { + { .start = 0x60004000, .end = 0x6000403f, .flags = IORESOURCE_MEM }, + { .start = 0x60004100, .end = 0x6000413f, .flags = IORESOURCE_MEM }, + { .start = 0x60004200, .end = 0x6000423f, .flags = IORESOURCE_MEM }, + { .start = 0x60004300, .end = 0x6000433f, .flags = IORESOURCE_MEM }, + { .start = 0x60004400, .end = 0x6000443f, .flags = IORESOURCE_MEM }, +}; + +static const struct of_device_id ictlr_matches[] = { + { .compatible = "nvidia,tegra20-ictlr", }, + { } +}; + +static const struct of_device_id gic_matches[] = { + { .compatible = "arm,cortex-a15-gic", }, + { .compatible = "arm,cortex-a9-gic", }, + { } +}; + void __init tegra_init_irq(void) { + struct device_node *np; + struct resource res; int i; - void __iomem *distbase; - distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); + np = of_find_matching_node(NULL, ictlr_matches); + if (np) { + for (i = 0; i < ARRAY_SIZE(ictlr_regs); i++) + if (of_address_to_resource(np, i, &res) == 0) + ictlr_regs[i] = res; + + of_node_put(np); + } + + np = of_find_matching_node(NULL, gic_matches); + if (np) { + if (of_address_to_resource(np, 0, &res) < 0) + res.start = res.end = 0; + + of_node_put(np); + } + + if (res.start == 0 || res.end == 0) { + res.start = 0x50041000; + res.end = 0x50041fff; + res.flags = IORESOURCE_MEM; + } + + distbase = ioremap_nocache(res.start, resource_size(&res)); num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f; if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) { - WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.", + WARN(1, "Too many (%d) interrupt controllers found. Maximum is %zu.", num_ictlrs, ARRAY_SIZE(ictlr_reg_base)); num_ictlrs = ARRAY_SIZE(ictlr_reg_base); } for (i = 0; i < num_ictlrs; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; + struct resource *regs = &ictlr_regs[i]; + void __iomem *ictlr; + + ictlr = ioremap_nocache(regs->start, resource_size(regs)); writel(~0, ictlr + ICTLR_CPU_IER_CLR); writel(0, ictlr + ICTLR_CPU_IEP_CLASS); + ictlr_reg_base[i] = ictlr; } gic_arch_extn.irq_ack = tegra_ack; @@ -286,9 +326,10 @@ void __init tegra_init_irq(void) * Check if there is a devicetree present, since the GIC will be * initialized elsewhere under DT. */ - if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); + if (!of_have_populated_dt()) { + void __iomem *cpubase = ioremap_nocache(0x50040000, 0x2000); + gic_init(0, 29, distbase, cpubase); + } tegra114_gic_cpu_pm_registration(); }