From patchwork Thu Jul 10 06:53:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 4521131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 44D079F1C4 for ; Thu, 10 Jul 2014 06:57:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 66243202F0 for ; Thu, 10 Jul 2014 06:57:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7ABD92024C for ; Thu, 10 Jul 2014 06:57:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58H0-0003UD-E6; Thu, 10 Jul 2014 06:56:06 +0000 Received: from szxga01-in.huawei.com ([119.145.14.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58G7-0001gs-LL for linux-arm-kernel@lists.infradead.org; Thu, 10 Jul 2014 06:55:13 +0000 Received: from 172.24.2.119 (EHLO SZXEML453-HUB.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BYO22135; Thu, 10 Jul 2014 14:54:24 +0800 (CST) Received: from localhost (10.177.27.142) by SZXEML453-HUB.china.huawei.com (10.82.67.196) with Microsoft SMTP Server id 14.3.158.1; Thu, 10 Jul 2014 14:54:18 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH v3 07/13] iommu/arm: Split arm_smmu_tlb_sync to reuse code Date: Thu, 10 Jul 2014 14:53:00 +0800 Message-ID: <1404975186-12032-8-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> References: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_235512_183640_8D310440 X-CRM114-Status: GOOD ( 13.38 ) X-Spam-Score: -1.4 (-) Cc: Zhen Lei X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP TLB sync wait is a common operation, should be shared by all SMMUs. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu-base.c | 15 +++++++++++++++ drivers/iommu/arm-smmu.c | 23 ++++++++++++----------- drivers/iommu/arm-smmu.h | 3 +++ 3 files changed, 30 insertions(+), 11 deletions(-) -- 1.8.0 diff --git a/drivers/iommu/arm-smmu-base.c b/drivers/iommu/arm-smmu-base.c index 4d1c511..53f7907 100644 --- a/drivers/iommu/arm-smmu-base.c +++ b/drivers/iommu/arm-smmu-base.c @@ -187,6 +187,21 @@ void __arm_smmu_free_bitmap(unsigned long *map, int idx) clear_bit(idx, map); } +void arm_smmu_tlb_sync_wait(struct arm_smmu_device *smmu) +{ + int count = 0; + + while (!smmu->hwdep_ops->tlb_sync_finished(smmu)) { + cpu_relax(); + if (++count == TLB_LOOP_TIMEOUT) { + dev_err_ratelimited(smmu->dev, + "TLB sync timed out -- SMMU may be deadlocked\n"); + return; + } + udelay(1); + } +} + void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, size_t size) { diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index d2fc14c..fa65c7c 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -223,23 +223,23 @@ #define FSYNR0_WNR (1 << 4) +static int arm_smmu_tlb_sync_finished(struct arm_smmu_device *smmu) +{ + u32 reg; + void __iomem *gr0_base = ARM_SMMU_GR0(smmu); + + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS); + + return !(reg & sTLBGSTATUS_GSACTIVE); +} + /* Wait for any pending TLB invalidations to complete */ static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) { - int count = 0; void __iomem *gr0_base = ARM_SMMU_GR0(smmu); writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); - while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) - & sTLBGSTATUS_GSACTIVE) { - cpu_relax(); - if (++count == TLB_LOOP_TIMEOUT) { - dev_err_ratelimited(smmu->dev, - "TLB sync timed out -- SMMU may be deadlocked\n"); - return; - } - udelay(1); - } + arm_smmu_tlb_sync_wait(smmu); } static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg) @@ -869,6 +869,7 @@ static int arm_smmu_device_unload(struct arm_smmu_device *smmu) } static struct smmu_hwdep_ops arm_smmu_hwdep_ops = { + .tlb_sync_finished = arm_smmu_tlb_sync_finished, .tlb_inv_context = arm_smmu_tlb_inv_context, .context_fault = arm_smmu_context_fault, .global_fault = arm_smmu_global_fault, diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 190f77c..8332ff0 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -209,6 +209,7 @@ struct arm_smmu_domain { /** * struct smmu_hwdep_ops - smmu hardware dependent ops + * @tlb_sync_finished: check whether tlb sync operation is finished * @tlb_inv_context: invalid smmu context bank tlb * @context_fault: context fault handler * @global_fault: global fault handler @@ -221,6 +222,7 @@ struct arm_smmu_domain { * @device_remove: turn off a smmu and reclaim associated resources */ struct smmu_hwdep_ops { + int (*tlb_sync_finished)(struct arm_smmu_device *smmu); void (*tlb_inv_context)(struct arm_smmu_cfg *cfg); irqreturn_t (*context_fault)(int irq, void *dev); irqreturn_t (*global_fault)(int irq, void *dev); @@ -237,6 +239,7 @@ struct smmu_hwdep_ops { extern int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end); extern void __arm_smmu_free_bitmap(unsigned long *map, int idx); +extern void arm_smmu_tlb_sync_wait(struct arm_smmu_device *smmu); extern struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu); extern void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, size_t size);