From patchwork Fri Jul 11 14:18:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 4535021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0650FBEEAA for ; Fri, 11 Jul 2014 14:22:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 316A420176 for ; Fri, 11 Jul 2014 14:22:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0ED272017A for ; Fri, 11 Jul 2014 14:22:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X5bgt-00080c-Aw; Fri, 11 Jul 2014 14:20:47 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X5bfi-0005bo-AP for linux-arm-kernel@lists.infradead.org; Fri, 11 Jul 2014 14:19:34 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 11 Jul 2014 07:18:41 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 11 Jul 2014 07:12:06 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 11 Jul 2014 07:12:06 -0700 Received: from mperttunen-lnx.Nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 11 Jul 2014 07:19:13 -0700 From: Mikko Perttunen To: , , , , Subject: [PATCH 5/8] of: Add Tegra124 EMC bindings Date: Fri, 11 Jul 2014 17:18:30 +0300 Message-ID: <1405088313-20048-6-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1405088313-20048-1-git-send-email-mperttunen@nvidia.com> References: <1405088313-20048-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140711_071934_377110_DC1DFE55 X-CRM114-Status: GOOD ( 11.87 ) X-Spam-Score: -0.7 (/) Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mikko Perttunen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add binding documentation for the nvidia,tegra124-emc device tree node. Signed-off-by: Mikko Perttunen --- .../bindings/memory-controllers/tegra-emc.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt new file mode 100644 index 0000000..2dde17e --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt @@ -0,0 +1,42 @@ +Tegra124 SoC EMC controller + +Required properties : +- compatible : "nvidia,tegra124-emc". +- reg : Should contain 1 or 2 entries: + - EMC register set + - MC register set : Required only if no node with + 'compatible = "nvidia,tegra124-mc"' exists. The MC register set + is first read from the MC node. If it doesn't exist, it is read + from this property. +- timings : Should contain 1 entry for each supported clock rate. + Entries should be named "timing@n" where n is a 0-based increasing + number. The timings must be listed in rate-ascending order. + +Required properties for timings : +- clock-frequency : Should contain the memory clock rate. +- nvidia,parent-clock-frequency : Should contain the rate of the EMC + clock's parent clock. +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + - emc-parent : EMC's parent clock. +- The following properties contain EMC timing characterization values: + - nvidia,emc-zcal-cnt-long + - nvidia,emc-auto-cal-interval + - nvidia,emc-ctt-term-ctrl + - nvidia,emc-cfg + - nvidia,emc-cfg-2 + - nvidia,emc-sel-dpd-ctrl + - nvidia,emc-cfg-dig-dll + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-auto-cal-config + - nvidia,emc-auto-cal-config2 + - nvidia,emc-auto-cal-config3 + - nvidia,emc-mode-reset + - nvidia,emc-mode-1 + - nvidia,emc-mode-2 + - nvidia,emc-mode-4 +- nvidia,emc-burst-data : EMC timing characterization data written to + EMC registers. +- nvidia,mc-burst-data : EMC timing characterization data written to + MC registers.