| Message ID | 1405115083-52977-7-git-send-email-s-anna@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
* Suman Anna <s-anna@ti.com> [140711 14:47]: > Add the hwmod data for the 13 instances of the system mailbox > IP in DRA7 SoC. The patch is needed for performing a soft-reset > while configuring the respective mailbox instance, otherwise is > a non-essential change for functionality. The modules are smart > idled on reset, and the IP module mode is hardware controlled. > > Cc: Rajendra Nayak <rnayak@ti.com> > Cc: Paul Walmsley <paul@pwsan.com> > Signed-off-by: Suman Anna <s-anna@ti.com> > --- > arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ > 1 file changed, 305 insertions(+) > > diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > index 20b4398..e35f5b1 100644 > --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { > }; > > /* > + * 'mailbox' class > + * > + */ > + > +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { > + .rev_offs = 0x0000, > + .sysc_offs = 0x0010, > + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | > + SYSC_HAS_SOFTRESET), > + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), > + .sysc_fields = &omap_hwmod_sysc_type2, > +}; > + > +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { > + .name = "mailbox", > + .sysc = &dra7xx_mailbox_sysc, > +}; Hmm I'm seeing just the following MAILBOX_SYSCONFIG in at least am57xx TRM: 31:4 RESERVED 3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved 1 RESERVED 0 SOFTRESET So it seems that SYSC_HAS_RESET_STATUS above is wrong? Can you guys please check. Regards, Tony
Hi Tony, On 07/15/2014 08:30 AM, Tony Lindgren wrote: > * Suman Anna <s-anna@ti.com> [140711 14:47]: >> Add the hwmod data for the 13 instances of the system mailbox >> IP in DRA7 SoC. The patch is needed for performing a soft-reset >> while configuring the respective mailbox instance, otherwise is >> a non-essential change for functionality. The modules are smart >> idled on reset, and the IP module mode is hardware controlled. >> >> Cc: Rajendra Nayak <rnayak@ti.com> >> Cc: Paul Walmsley <paul@pwsan.com> >> Signed-off-by: Suman Anna <s-anna@ti.com> >> --- >> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ >> 1 file changed, 305 insertions(+) >> >> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c >> index 20b4398..e35f5b1 100644 >> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c >> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c >> @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { >> }; >> >> /* >> + * 'mailbox' class >> + * >> + */ >> + >> +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { >> + .rev_offs = 0x0000, >> + .sysc_offs = 0x0010, >> + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | >> + SYSC_HAS_SOFTRESET), >> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), >> + .sysc_fields = &omap_hwmod_sysc_type2, >> +}; >> + >> +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { >> + .name = "mailbox", >> + .sysc = &dra7xx_mailbox_sysc, >> +}; > > Hmm I'm seeing just the following MAILBOX_SYSCONFIG in at least > am57xx TRM: > > 31:4 RESERVED > 3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved > 1 RESERVED > 0 SOFTRESET > > So it seems that SYSC_HAS_RESET_STATUS above is wrong? Can you guys > please check. The same SOFTRESET bit is used for both triggering the softreset and reading the reset done status. Once you write a 1 to trigger a reset, the bit will be cleared once the reset is done. This is no different from OMAP4. The logic in _wait_softreset_complete in omap_hwmod.c was already designed to work with this properly. regards Suman
* Suman Anna <s-anna@ti.com> [140715 09:59]: > Hi Tony, > > On 07/15/2014 08:30 AM, Tony Lindgren wrote: > > * Suman Anna <s-anna@ti.com> [140711 14:47]: > >> Add the hwmod data for the 13 instances of the system mailbox > >> IP in DRA7 SoC. The patch is needed for performing a soft-reset > >> while configuring the respective mailbox instance, otherwise is > >> a non-essential change for functionality. The modules are smart > >> idled on reset, and the IP module mode is hardware controlled. > >> > >> Cc: Rajendra Nayak <rnayak@ti.com> > >> Cc: Paul Walmsley <paul@pwsan.com> > >> Signed-off-by: Suman Anna <s-anna@ti.com> > >> --- > >> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ > >> 1 file changed, 305 insertions(+) > >> > >> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > >> index 20b4398..e35f5b1 100644 > >> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > >> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > >> @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { > >> }; > >> > >> /* > >> + * 'mailbox' class > >> + * > >> + */ > >> + > >> +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { > >> + .rev_offs = 0x0000, > >> + .sysc_offs = 0x0010, > >> + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | > >> + SYSC_HAS_SOFTRESET), > >> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), > >> + .sysc_fields = &omap_hwmod_sysc_type2, > >> +}; > >> + > >> +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { > >> + .name = "mailbox", > >> + .sysc = &dra7xx_mailbox_sysc, > >> +}; > > > > Hmm I'm seeing just the following MAILBOX_SYSCONFIG in at least > > am57xx TRM: > > > > 31:4 RESERVED > > 3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved > > 1 RESERVED > > 0 SOFTRESET > > > > So it seems that SYSC_HAS_RESET_STATUS above is wrong? Can you guys > > please check. > > The same SOFTRESET bit is used for both triggering the softreset and > reading the reset done status. Once you write a 1 to trigger a reset, > the bit will be cleared once the reset is done. This is no different > from OMAP4. The logic in _wait_softreset_complete in omap_hwmod.c was > already designed to work with this properly. Oh OK, I guess I got it confused with SYSS_HAS_RESET_STATUS. Paul, want to ack this one if no other issues? I can then set this series into a branch against -rc1 that we can all merge in as needed as it seems that the driver changes may need this branch as a base too. Regards, Tony
* Tony Lindgren <tony@atomide.com> [140716 00:10]: > * Suman Anna <s-anna@ti.com> [140715 09:59]: > > Hi Tony, > > > > On 07/15/2014 08:30 AM, Tony Lindgren wrote: > > > * Suman Anna <s-anna@ti.com> [140711 14:47]: > > >> Add the hwmod data for the 13 instances of the system mailbox > > >> IP in DRA7 SoC. The patch is needed for performing a soft-reset > > >> while configuring the respective mailbox instance, otherwise is > > >> a non-essential change for functionality. The modules are smart > > >> idled on reset, and the IP module mode is hardware controlled. > > >> > > >> Cc: Rajendra Nayak <rnayak@ti.com> > > >> Cc: Paul Walmsley <paul@pwsan.com> > > >> Signed-off-by: Suman Anna <s-anna@ti.com> > > >> --- > > >> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ > > >> 1 file changed, 305 insertions(+) > > >> > > >> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > > >> index 20b4398..e35f5b1 100644 > > >> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > > >> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > > >> @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { > > >> }; > > >> > > >> /* > > >> + * 'mailbox' class > > >> + * > > >> + */ > > >> + > > >> +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { > > >> + .rev_offs = 0x0000, > > >> + .sysc_offs = 0x0010, > > >> + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | > > >> + SYSC_HAS_SOFTRESET), > > >> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), > > >> + .sysc_fields = &omap_hwmod_sysc_type2, > > >> +}; > > >> + > > >> +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { > > >> + .name = "mailbox", > > >> + .sysc = &dra7xx_mailbox_sysc, > > >> +}; > > > > > > Hmm I'm seeing just the following MAILBOX_SYSCONFIG in at least > > > am57xx TRM: > > > > > > 31:4 RESERVED > > > 3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved > > > 1 RESERVED > > > 0 SOFTRESET > > > > > > So it seems that SYSC_HAS_RESET_STATUS above is wrong? Can you guys > > > please check. > > > > The same SOFTRESET bit is used for both triggering the softreset and > > reading the reset done status. Once you write a 1 to trigger a reset, > > the bit will be cleared once the reset is done. This is no different > > from OMAP4. The logic in _wait_softreset_complete in omap_hwmod.c was > > already designed to work with this properly. > > Oh OK, I guess I got it confused with SYSS_HAS_RESET_STATUS. Paul, > want to ack this one if no other issues? I can then set this series > into a branch against -rc1 that we can all merge in as needed as > it seems that the driver changes may need this branch as a base too. I have applied these into omap-for-v3.17/mailbox and merged also into omap-for-v3.17/soc. Regards, Tony
On 07/23/2014 04:24 AM, Tony Lindgren wrote: > * Tony Lindgren <tony@atomide.com> [140716 00:10]: >> * Suman Anna <s-anna@ti.com> [140715 09:59]: >>> Hi Tony, >>> >>> On 07/15/2014 08:30 AM, Tony Lindgren wrote: >>>> * Suman Anna <s-anna@ti.com> [140711 14:47]: >>>>> Add the hwmod data for the 13 instances of the system mailbox >>>>> IP in DRA7 SoC. The patch is needed for performing a soft-reset >>>>> while configuring the respective mailbox instance, otherwise is >>>>> a non-essential change for functionality. The modules are smart >>>>> idled on reset, and the IP module mode is hardware controlled. >>>>> >>>>> Cc: Rajendra Nayak <rnayak@ti.com> >>>>> Cc: Paul Walmsley <paul@pwsan.com> >>>>> Signed-off-by: Suman Anna <s-anna@ti.com> >>>>> --- >>>>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ >>>>> 1 file changed, 305 insertions(+) >>>>> >>>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c >>>>> index 20b4398..e35f5b1 100644 >>>>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c >>>>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c >>>>> @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { >>>>> }; >>>>> >>>>> /* >>>>> + * 'mailbox' class >>>>> + * >>>>> + */ >>>>> + >>>>> +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { >>>>> + .rev_offs = 0x0000, >>>>> + .sysc_offs = 0x0010, >>>>> + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | >>>>> + SYSC_HAS_SOFTRESET), >>>>> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), >>>>> + .sysc_fields = &omap_hwmod_sysc_type2, >>>>> +}; >>>>> + >>>>> +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { >>>>> + .name = "mailbox", >>>>> + .sysc = &dra7xx_mailbox_sysc, >>>>> +}; >>>> >>>> Hmm I'm seeing just the following MAILBOX_SYSCONFIG in at least >>>> am57xx TRM: >>>> >>>> 31:4 RESERVED >>>> 3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved >>>> 1 RESERVED >>>> 0 SOFTRESET >>>> >>>> So it seems that SYSC_HAS_RESET_STATUS above is wrong? Can you guys >>>> please check. >>> >>> The same SOFTRESET bit is used for both triggering the softreset and >>> reading the reset done status. Once you write a 1 to trigger a reset, >>> the bit will be cleared once the reset is done. This is no different >>> from OMAP4. The logic in _wait_softreset_complete in omap_hwmod.c was >>> already designed to work with this properly. >> >> Oh OK, I guess I got it confused with SYSS_HAS_RESET_STATUS. Paul, >> want to ack this one if no other issues? I can then set this series >> into a branch against -rc1 that we can all merge in as needed as >> it seems that the driver changes may need this branch as a base too. > > I have applied these into omap-for-v3.17/mailbox and merged also > into omap-for-v3.17/soc. > Thank you, Tony. regards Suman
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 20b4398..e35f5b1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { }; /* + * 'mailbox' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &dra7xx_mailbox_sysc, +}; + +/* mailbox1 */ +static struct omap_hwmod dra7xx_mailbox1_hwmod = { + .name = "mailbox1", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox2 */ +static struct omap_hwmod dra7xx_mailbox2_hwmod = { + .name = "mailbox2", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox3 */ +static struct omap_hwmod dra7xx_mailbox3_hwmod = { + .name = "mailbox3", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox4 */ +static struct omap_hwmod dra7xx_mailbox4_hwmod = { + .name = "mailbox4", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox5 */ +static struct omap_hwmod dra7xx_mailbox5_hwmod = { + .name = "mailbox5", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox6 */ +static struct omap_hwmod dra7xx_mailbox6_hwmod = { + .name = "mailbox6", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox7 */ +static struct omap_hwmod dra7xx_mailbox7_hwmod = { + .name = "mailbox7", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox8 */ +static struct omap_hwmod dra7xx_mailbox8_hwmod = { + .name = "mailbox8", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox9 */ +static struct omap_hwmod dra7xx_mailbox9_hwmod = { + .name = "mailbox9", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox10 */ +static struct omap_hwmod dra7xx_mailbox10_hwmod = { + .name = "mailbox10", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox11 */ +static struct omap_hwmod dra7xx_mailbox11_hwmod = { + .name = "mailbox11", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox12 */ +static struct omap_hwmod dra7xx_mailbox12_hwmod = { + .name = "mailbox12", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox13 */ +static struct omap_hwmod dra7xx_mailbox13_hwmod = { + .name = "mailbox13", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mcspi' class * */ @@ -2246,6 +2434,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> mailbox1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_mailbox1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox7_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox8_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox9 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox9_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox10 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox10_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox11 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox11_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox12_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox13 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox13_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> mcspi1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { .master = &dra7xx_l4_per1_hwmod, @@ -2662,6 +2954,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_l4_cfg__mailbox1, + &dra7xx_l4_per3__mailbox2, + &dra7xx_l4_per3__mailbox3, + &dra7xx_l4_per3__mailbox4, + &dra7xx_l4_per3__mailbox5, + &dra7xx_l4_per3__mailbox6, + &dra7xx_l4_per3__mailbox7, + &dra7xx_l4_per3__mailbox8, + &dra7xx_l4_per3__mailbox9, + &dra7xx_l4_per3__mailbox10, + &dra7xx_l4_per3__mailbox11, + &dra7xx_l4_per3__mailbox12, + &dra7xx_l4_per3__mailbox13, &dra7xx_l4_per1__mcspi1, &dra7xx_l4_per1__mcspi2, &dra7xx_l4_per1__mcspi3,
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)