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Fri, 18 Jul 2014 08:26:40 -0500 (CDT) Received: from SATLEXDAG03.amd.com (10.181.40.7) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.2.328.9; Fri, 18 Jul 2014 08:26:48 -0500 Received: from ssuthiku-fedora-lt.amd.com (10.180.168.240) by satlexdag03.amd.com (10.181.40.7) with Microsoft SMTP Server id 14.2.328.9; Fri, 18 Jul 2014 09:26:41 -0400 From: To: , , Subject: [PATCH] irqchip: gicv2m: Clean up logic for detecting MSI support Date: Fri, 18 Jul 2014 08:26:36 -0500 Message-ID: <1405689996-3601-1-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.0 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(428002)(199002)(189002)(46102001)(83322001)(19580405001)(86362001)(93916002)(19580395003)(77982001)(86152002)(97736001)(79102001)(4396001)(87936001)(87286001)(229853001)(107046002)(74502001)(74662001)(84676001)(101416001)(99396002)(31966008)(92726001)(92566001)(2201001)(102836001)(50986999)(104166001)(88136002)(53416004)(85852003)(21056001)(50226001)(83072002)(76482001)(62966002)(89996001)(50466002)(80022001)(64706001)(85306003)(77096002)(77156001)(105586002)(106466001)(44976005)(20776003)(47776003)(95666004)(48376002)(36756003)(33646002)(81342001)(81542001); DIR:OUT; SFP:; SCL:1; SRVR:BN1PR02MB039; H:atltwp01.amd.com; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 02760F0D1C Received-SPF: None (: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; X-OriginatorOrg: amd4.onmicrosoft.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140718_062710_161282_0646A563 X-CRM114-Status: GOOD ( 12.33 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, pawel.moll@arm.com, linux-doc@vger.kernel.org, Marc Zyngier , Catalin.Marinas@arm.com, Harish.Kasiviswanathan@amd.com, linux-kernel@vger.kernel.org, Will.Deacon@arm.com, Suravee Suthikulpanit , linux-pci@vger.kernel.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Suravee Suthikulpanit It's not quite clear that msi-controller is already checked by of_msi_chip_add. So, this patch add a note to clarify. Also, clean up redundant logic and unnecessary pr_info. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Suravee Suthikulpanit --- Note: This patch is created against irqchip/gic branch. drivers/irqchip/irq-gic-v2m.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index e54ca1d..94ed8d6 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -235,15 +235,15 @@ gicv2m_of_init(struct device_node *node, struct device_node *parent) gic->msi_chip.teardown_irq = gicv2m_teardown_msi_irq; ret = of_pci_msi_chip_add(&gic->msi_chip); if (ret) { - /* MSI is optional and not supported here */ - pr_info("GICv2m: MSI is not supported.\n"); + /* + * Note: msi-controller is checked in of_pci_msi_chip_add(). + * MSI support is optional, and enabled only if msi-controller + * is specified. Hence, return 0. + */ return 0; } - ret = gicv2m_msi_init(node, &gic->v2m_data); - if (ret) - return ret; - return ret; + return gicv2m_msi_init(node, &gic->v2m_data); } IRQCHIP_DECLARE(arm_gic_400_v2m, "arm,gic-400-v2m", gicv2m_of_init);