From patchwork Mon Jul 21 15:38:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tuomas Tynkkynen X-Patchwork-Id: 4596731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D0406C0515 for ; Mon, 21 Jul 2014 15:43:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 08575200DB for ; Mon, 21 Jul 2014 15:43:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A57F5200E9 for ; Mon, 21 Jul 2014 15:43:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X9FiC-0005mj-Df; Mon, 21 Jul 2014 15:41:12 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X9FhQ-0004Aq-OJ for linux-arm-kernel@lists.infradead.org; Mon, 21 Jul 2014 15:40:26 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 21 Jul 2014 08:39:56 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 21 Jul 2014 08:28:22 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 21 Jul 2014 08:28:22 -0700 Received: from ttynkkynen-lnx.Nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.342.0; Mon, 21 Jul 2014 08:40:02 -0700 From: Tuomas Tynkkynen To: , , , Subject: [PATCH v2 07/16] clk: tegra: Add DFLL DVCO reset control for Tegra124 Date: Mon, 21 Jul 2014 18:38:53 +0300 Message-ID: <1405957142-19416-8-git-send-email-ttynkkynen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> References: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140721_084024_841276_5EE37C35 X-CRM114-Status: GOOD ( 13.16 ) X-Spam-Score: -0.0 (/) Cc: devicetree@vger.kernel.org, Prashant Gaikwad , Mike Turquette , Stephen Warren , Viresh Kumar , Peter De Schrijver , "Rafael J. Wysocki" , Thierry Reding , Tuomas Tynkkynen , Paul Walmsley X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paul Walmsley The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley [ttynkkynen: ported to tegra124 from tegra114] Signed-off-by: Tuomas Tynkkynen --- v2 changes: - none drivers/clk/tegra/clk-tegra124.c | 47 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 50 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 80efe51..77fbf38 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -31,6 +31,9 @@ #define CLK_SOURCE_CSITE 0x1d4 #define CLK_SOURCE_EMC 0x19c +#define RST_DFLL_DVCO 0x2f4 +#define DVFS_DFLL_RESET_SHIFT 0 + #define PLLC_BASE 0x80 #define PLLC_OUT 0x84 #define PLLC_MISC2 0x88 @@ -1378,6 +1381,50 @@ static void __init tegra124_clock_apply_init_table(void) tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX); } +/** + * tegra124_car_barrier - wait for pending writes to the CAR to complete + * + * Wait for any outstanding writes to the CAR MMIO space from this CPU + * to complete before continuing execution. No return value. + */ +static void tegra124_car_barrier(void) +{ + readl_relaxed(clk_base + RST_DFLL_DVCO); +} + +/** + * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset + * + * Assert the reset line of the DFLL's DVCO. No return value. + */ +void tegra124_clock_assert_dfll_dvco_reset(void) +{ + u32 v; + + v = readl_relaxed(clk_base + RST_DFLL_DVCO); + v |= (1 << DVFS_DFLL_RESET_SHIFT); + writel_relaxed(v, clk_base + RST_DFLL_DVCO); + tegra124_car_barrier(); +} +EXPORT_SYMBOL(tegra124_clock_assert_dfll_dvco_reset); + +/** + * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset + * + * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to + * operate. No return value. + */ +void tegra124_clock_deassert_dfll_dvco_reset(void) +{ + u32 v; + + v = readl_relaxed(clk_base + RST_DFLL_DVCO); + v &= ~(1 << DVFS_DFLL_RESET_SHIFT); + writel_relaxed(v, clk_base + RST_DFLL_DVCO); + tegra124_car_barrier(); +} +EXPORT_SYMBOL(tegra124_clock_deassert_dfll_dvco_reset); + static void __init tegra124_clock_init(struct device_node *np) { struct device_node *node; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 16ec8d6..4b3f3d0 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -627,6 +627,9 @@ void tegra114_clock_tune_cpu_trimmers_init(void); void tegra114_clock_assert_dfll_dvco_reset(void); void tegra114_clock_deassert_dfll_dvco_reset(void); +void tegra124_clock_assert_dfll_dvco_reset(void); +void tegra124_clock_deassert_dfll_dvco_reset(void); + typedef void (*tegra_clk_apply_init_table_func)(void); extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;