From patchwork Sat Jul 26 23:18:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 4630531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 084359F2B8 for ; Sat, 26 Jul 2014 23:21:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E16682017D for ; Sat, 26 Jul 2014 23:21:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 97E5A2015E for ; Sat, 26 Jul 2014 23:21:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBBEK-0005RJ-1i; Sat, 26 Jul 2014 23:18:20 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBBDt-0005C5-JX for linux-arm-kernel@bombadil.infradead.org; Sat, 26 Jul 2014 23:17:53 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBBDq-0003Zv-T5 for linux-arm-kernel@lists.infradead.org; Sat, 26 Jul 2014 23:17:51 +0000 Received: from ip9234425c.dynamic.kabel-deutschland.de ([146.52.66.92] helo=diego.lan) by gloria.sntech.de with esmtpsa (TLS1.1:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1XBBD7-0004nt-Gf; Sun, 27 Jul 2014 01:17:05 +0200 From: Heiko Stuebner To: arnd@arndb.de, linux-arm-kernel@lists.infradead.org, olof@lixom.net, devicetree@vger.kernel.org, b.galvani@gmail.com, max.schwarz@online.de Subject: [PATCH v2 01/15] ARM: dts: rockchip: add cru nodes and update device clocks to use it Date: Sun, 27 Jul 2014 01:18:17 +0200 Message-Id: <1406416711-28006-2-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1406416711-28006-1-git-send-email-heiko@sntech.de> References: <1406416711-28006-1-git-send-email-heiko@sntech.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140727_001750_962253_A73421CD X-CRM114-Status: GOOD ( 11.27 ) X-Spam-Score: -1.9 (-) Cc: Heiko Stuebner X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and also updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes. Signed-off-by: Heiko Stuebner Acked-by: Max Schwarz Tested-by: Max Schwarz --- arch/arm/boot/dts/rk3066a.dtsi | 28 +++++++++++++++++++--------- arch/arm/boot/dts/rk3188.dtsi | 18 ++++++++++++++---- arch/arm/boot/dts/rk3xxx.dtsi | 16 ++++++++-------- 3 files changed, 41 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4387cfd..15c81d2 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3066a-clocks.dtsi" @@ -45,7 +46,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; interrupts = ; - clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; clock-names = "timer", "pclk"; }; @@ -53,7 +54,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2003a000 0x100>; interrupts = ; - clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; clock-names = "timer", "pclk"; }; @@ -61,7 +62,7 @@ compatible = "snps,dw-apb-timer-osc"; reg = <0x2000e000 0x100>; interrupts = ; - clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; clock-names = "timer", "pclk"; }; @@ -78,6 +79,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; @@ -89,7 +99,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20034000 0x100>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -102,7 +112,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -115,7 +125,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -128,7 +138,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; @@ -141,7 +151,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; - clocks = <&clk_gates8 13>; + clocks = <&cru PCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; @@ -154,7 +164,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2000a000 0x100>; interrupts = ; - clocks = <&clk_gates8 15>; + clocks = <&cru PCLK_GPIO6>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 238c996..bf0741a 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3188-clocks.dtsi" @@ -74,6 +75,15 @@ }; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -87,7 +97,7 @@ compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -100,7 +110,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -113,7 +123,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -126,7 +136,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 2adf1cc9e..b47d5fe 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -60,14 +60,14 @@ compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; interrupts = ; - clocks = <&dummy150m>; + clocks = <&cru CORE_PERI>; }; local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; interrupts = ; - clocks = <&dummy150m>; + clocks = <&cru CORE_PERI>; }; uart0: serial@10124000 { @@ -76,7 +76,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 8>; + clocks = <&cru SCLK_UART0>; status = "disabled"; }; @@ -86,7 +86,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 10>; + clocks = <&cru SCLK_UART1>; status = "disabled"; }; @@ -96,7 +96,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 12>; + clocks = <&cru SCLK_UART2>; status = "disabled"; }; @@ -106,7 +106,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clocks = <&clk_gates1 14>; + clocks = <&cru SCLK_UART3>; status = "disabled"; }; @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <0>; - clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; status = "disabled"; @@ -130,7 +130,7 @@ #address-cells = <1>; #size-cells = <0>; - clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; status = "disabled";