From patchwork Fri Aug 1 05:58:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 4660641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0DA8C0338 for ; Fri, 1 Aug 2014 06:02:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1DD66201F4 for ; Fri, 1 Aug 2014 06:02:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29129201ED for ; Fri, 1 Aug 2014 06:02:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XD5rV-00045N-K6; Fri, 01 Aug 2014 05:58:41 +0000 Received: from mail-pa0-f73.google.com ([209.85.220.73]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XD5rS-00044t-Pr for linux-arm-kernel@lists.infradead.org; Fri, 01 Aug 2014 05:58:39 +0000 Received: by mail-pa0-f73.google.com with SMTP id kx10so684075pab.0 for ; Thu, 31 Jul 2014 22:58:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TPpxDl1R0aPhHaJfBb+nyDghIlMDt3T9jYDt71tr80Q=; b=UXUMfG0YqsFDCBE7rCRQjI1DgX+NgOtkdreKbbtee5mpRulqYgDvfSmf+ghn3EIB+D YlmUNsDxcNmfx8XFeogRm15wi9kCaILNkzJuJ/t1yVSLXIftXVlff0dDy3hH0JYqH3mv FV4I54lJ4JD+H+IIc6isFiderbwpdalYQF7QCm+QteXcOnWUbIwpce5CPI57rvwuYHFc wvFHniL7B06q0xWN1XKItFb0tHTYzkXIXQr6xSZ+V9BUIwoDuGs5bLtlnXRHYBXP3Fud Km5aLtNx0wx1qanNst0rvX/SMLl20r3jIQnMgHaeomH3F4ZW5RuEPwu38CppEuOyCHLH eUXQ== X-Gm-Message-State: ALoCoQluVDF47fFZvPRqg1gqAQpD72lKJ2UInHfphdEUfRHWFGSc2D49lr5ygysujuBKskrrtQMb X-Received: by 10.66.252.6 with SMTP id zo6mr1395555pac.40.1406872693417; Thu, 31 Jul 2014 22:58:13 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id y50si483942yhk.4.2014.07.31.22.58.13 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 31 Jul 2014 22:58:13 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com (sonnyrao.mtv.corp.google.com [172.22.162.1]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 3343031C3E3; Thu, 31 Jul 2014 22:58:13 -0700 (PDT) Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id CA7D8A09B9; Thu, 31 Jul 2014 22:58:12 -0700 (PDT) From: Sonny Rao To: Heiko Stuebner Subject: [PATCH v2] pinctrl: rockchip: fix rk3288 gpio0 configuration Date: Thu, 31 Jul 2014 22:58:00 -0700 Message-Id: <1406872680-14641-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.0.0.526.g5318336 In-Reply-To: <1543632.JNPYWq24Lp@diego> References: <1543632.JNPYWq24Lp@diego> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140731_225838_863167_56BD4ED6 X-CRM114-Status: GOOD ( 12.76 ) X-Spam-Score: -2.0 (--) Cc: Sonny Rao , Linus Walleij , eddie.cai@rock-chips.com, dianders@chromium.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On rk3288, for gpio bank 0, the registers which configure pull-up, iomux, and drive strength don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio in that bank. The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of bank0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered. Signed-off-by: Sonny Rao Reviewed-by: Heiko Stuebner Reviewed-by: Doug Anderson --- v2: rebase onto latest pinctrl with drive strength and fix this bug on iomux and drive strength as well. drivers/pinctrl/pinctrl-rockchip.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index c15f7f9..4ff5dc3 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -438,7 +438,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) int reg, ret, mask; unsigned long flags; u8 bit; - u32 data; + u32 data, rmask; if (iomux_num > 3) return -EINVAL; @@ -478,8 +478,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) spin_lock_irqsave(&bank->slock, flags); data = (mask << (bit + 16)); + rmask = data | (data >> 16); data |= (mux & mask) << bit; - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); spin_unlock_irqrestore(&bank->slock, flags); @@ -634,7 +635,7 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, struct regmap *regmap; unsigned long flags; int reg, ret, i; - u32 data; + u32 data, rmask; u8 bit; rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); @@ -657,9 +658,10 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, /* enable the write to the equivalent lower bits */ data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); data |= (ret << bit); - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); spin_unlock_irqrestore(&bank->slock, flags); return ret; @@ -722,7 +724,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, int reg, ret; unsigned long flags; u8 bit; - u32 data; + u32 data, rmask; dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); @@ -750,6 +752,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, /* enable the write to the equivalent lower bits */ data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); switch (pull) { case PIN_CONFIG_BIAS_DISABLE: @@ -770,7 +773,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, return -EINVAL; } - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); spin_unlock_irqrestore(&bank->slock, flags); break;