From patchwork Mon Aug 4 00:47:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olav Haugan X-Patchwork-Id: 4666511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8F977C0338 for ; Mon, 4 Aug 2014 00:50:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E586D201CE for ; Mon, 4 Aug 2014 00:50:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34D8D200F2 for ; Mon, 4 Aug 2014 00:50:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XE6Rr-0005Wc-3R; Mon, 04 Aug 2014 00:48:23 +0000 Received: from smtp.codeaurora.org ([198.145.11.231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XE6Rj-0005UB-Lz for linux-arm-kernel@lists.infradead.org; Mon, 04 Aug 2014 00:48:16 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id EBEF813F64F; Mon, 4 Aug 2014 00:47:51 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id DF72913F655; Mon, 4 Aug 2014 00:47:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from ohaugan-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: ohaugan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7419713F64F; Mon, 4 Aug 2014 00:47:51 +0000 (UTC) From: Olav Haugan To: will.deacon@arm.com Subject: [PATCH v1 1/2] iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1 Date: Sun, 3 Aug 2014 17:47:43 -0700 Message-Id: <1407113264-23426-2-git-send-email-ohaugan@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1407113264-23426-1-git-send-email-ohaugan@codeaurora.org> References: <1407113264-23426-1-git-send-email-ohaugan@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140803_174815_741074_EA2528C7 X-CRM114-Status: GOOD ( 12.55 ) X-Spam-Score: -0.7 (/) Cc: Olav Haugan , linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, mitchelh@codeaurora.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Stage-1 context bank does not have SMMU_CBn_TCR[SL0] field. SL0 field is only applicable to stage-2 context banks. Signed-off-by: Olav Haugan --- drivers/iommu/arm-smmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ff6633d..a83ca6a 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -833,6 +833,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); break; } + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + } else { reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; } @@ -843,8 +845,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= TTBCR_EAE | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | - (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | - (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); /* MAIR0 (stage-1 only) */