From patchwork Tue Aug 5 14:58:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yingjoe Chen X-Patchwork-Id: 4679561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EEAAEC0338 for ; Tue, 5 Aug 2014 15:07:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D3C6C2018B for ; Tue, 5 Aug 2014 15:07:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2CF92018E for ; Tue, 5 Aug 2014 15:07:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XEgHv-0007La-Ot; Tue, 05 Aug 2014 15:04:31 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XEgHg-0007Ej-6S for linux-arm-kernel@lists.infradead.org; Tue, 05 Aug 2014 15:04:25 +0000 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 609326988; Tue, 05 Aug 2014 22:58:14 +0800 Received: from mtksdtcf02.mediatek.inc (10.21.12.142) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Tue, 5 Aug 2014 22:58:13 +0800 From: Joe.C To: , Subject: [PATCH 1/3] irqchip: gic: Change irq type check when extension is present Date: Tue, 5 Aug 2014 22:58:08 +0800 Message-ID: <1407250690-2858-2-git-send-email-srv_yingjoe.chen@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1407250690-2858-1-git-send-email-srv_yingjoe.chen@mediatek.com> References: <1407250690-2858-1-git-send-email-srv_yingjoe.chen@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140805_080416_447236_4D10D4B4 X-CRM114-Status: GOOD ( 11.94 ) X-Spam-Score: 1.3 (+) Cc: yingjoe.chen@gmail.com, srv_heupstream@mediatek.com, hc.yen@mediatek.com, yh.chen@mediatek.com, olof@lixom.net, nathan.chung@mediatek.com, Matthias Brugger , eddie.huang@mediatek.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Joe.C" GIC supports the combination with external extensions. But this is not reflected in the checks of the interrupt type flag. This patch allows interrupt types other than the one supported by GIC, if an architecture extension is present and supports them. Signed-off-by: Joe.C --- drivers/irqchip/irq-gic.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 57d165e..66485ab 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -194,23 +194,32 @@ static int gic_set_type(struct irq_data *d, unsigned int type) u32 confoff = (gicirq / 16) * 4; bool enabled = false; u32 val; + int ret = 0; /* Interrupt configuration for SGIs can't be changed */ if (gicirq < 16) return -EINVAL; - if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) - return -EINVAL; - raw_spin_lock(&irq_controller_lock); - if (gic_arch_extn.irq_set_type) - gic_arch_extn.irq_set_type(d, type); + if (gic_arch_extn.irq_set_type) { + ret = gic_arch_extn.irq_set_type(d, type); + if (ret) + goto out; + } else if (type != IRQ_TYPE_LEVEL_HIGH && + type != IRQ_TYPE_EDGE_RISING) { + ret = -EINVAL; + goto out; + } val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); - if (type == IRQ_TYPE_LEVEL_HIGH) + /* Check for both edge and level here, so we can support GIC irq + polarity extension in gic_arch_extn.irq_set_type. If arch + doesn't support polarity extension, the check above will reject + improper type. */ + if (type & IRQ_TYPE_LEVEL_MASK) val &= ~confmask; - else if (type == IRQ_TYPE_EDGE_RISING) + else if (type & IRQ_TYPE_EDGE_BOTH) val |= confmask; /* @@ -226,10 +235,10 @@ static int gic_set_type(struct irq_data *d, unsigned int type) if (enabled) writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); - +out: raw_spin_unlock(&irq_controller_lock); - return 0; + return ret; } static int gic_retrigger(struct irq_data *d)