From patchwork Wed Aug 6 15:46:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 4687101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C1F5CC0338 for ; Wed, 6 Aug 2014 15:48:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C070C20107 for ; Wed, 6 Aug 2014 15:48:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B5CA820103 for ; Wed, 6 Aug 2014 15:48:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XF3QD-00055l-5K; Wed, 06 Aug 2014 15:46:37 +0000 Received: from mail-wi0-f178.google.com ([209.85.212.178]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XF3QA-0004wr-Kk for linux-arm-kernel@lists.infradead.org; Wed, 06 Aug 2014 15:46:35 +0000 Received: by mail-wi0-f178.google.com with SMTP id hi2so3496008wib.17 for ; Wed, 06 Aug 2014 08:46:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WkIFIzV+oAAkfsj8R+XxSzev5e/FYqpBVcMA91b9h1Y=; b=iTNOvwdXwIic98IGVXg3jFeYYibVp5JJ/tGi2YXZfKNFnUK6F01eYPs4GCgbceuS01 j74N3iSvQW7vgv5lHq4iWsAJM+BuuV2LEtbF27SRUBCu4C0118uOgkOPZ6IPZdeXfznI zaUGUZhj1jOI7QJNouaNBDWqH0pQr+SsLcqdJEevybWeXr8V15GOF8C9CnrF15T9jOtH h4gj9r3DOzmPMuQ14YRq01Jv8cadi8SudX/xQzUpQKBldlcufkPkMn/QDfOQjnGFaxIS 8Tmgu3K6oOapYcAD1Yp0x6ARWOHRmmdAHcow+TpayMDACnk4V31VjTfcrMbCByYOhg1T A7Lw== X-Gm-Message-State: ALoCoQnWN8U56vYlhWzIU3btYiRVzhWp+8WYt5zQb/cb2OlhRUbNKnF7CEkj/DPBe6W6jnRdMqYw X-Received: by 10.180.92.38 with SMTP id cj6mr17519551wib.64.1407339972019; Wed, 06 Aug 2014 08:46:12 -0700 (PDT) Received: from ards-macbook-pro.local ([188.252.209.16]) by mx.google.com with ESMTPSA id xn12sm19455514wib.13.2014.08.06.08.46.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 Aug 2014 08:46:11 -0700 (PDT) From: Ard Biesheuvel To: will.deacon@arm.com, mark.rutland@arm.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] arm64: add helper functions to read I-cache attributes Date: Wed, 6 Aug 2014 17:46:05 +0200 Message-Id: <1407339966-29351-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140806_084634_823066_987B459D X-CRM114-Status: GOOD ( 11.19 ) X-Spam-Score: -0.7 (/) Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds helper functions and #defines to to read the line size and the number of sets from the level 1 instruction cache. Signed-off-by: Ard Biesheuvel --- v3: add WARN_ON(preemptible()), move icache_get_ccsidr() to cpuinfo.c to prevent #include header recursion hell v2: put () around macro args, use 64-bit types for asm() mrs/msr calls arch/arm64/include/asm/cachetype.h | 20 ++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 14 ++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index 7a2e0762cb40..4c631a0a3609 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -39,6 +39,26 @@ extern unsigned long __icache_flags; +#define CCSIDR_EL1_LINESIZE_MASK 0x7 +#define CCSIDR_EL1_LINESIZE(x) ((x) & CCSIDR_EL1_LINESIZE_MASK) + +#define CCSIDR_EL1_NUMSETS_SHIFT 13 +#define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT) +#define CCSIDR_EL1_NUMSETS(x) \ + (((x) & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT) + +extern u64 __attribute_const__ icache_get_ccsidr(void); + +static inline int icache_get_linesize(void) +{ + return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr()); +} + +static inline int icache_get_numsets(void) +{ + return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr()); +} + /* * Whilst the D-side always behaves as PIPT on AArch64, aliasing is * permitted in the I-cache. diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index f798f66634af..319255ff536d 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -20,8 +20,10 @@ #include #include +#include #include #include +#include #include #include @@ -190,3 +192,15 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; } + +u64 __attribute_const__ icache_get_ccsidr(void) +{ + u64 ccsidr; + + WARN_ON(preemptible()); + + /* Select L1 I-cache and read its size ID register */ + asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1" + : "=r"(ccsidr) : "r"(1L)); + return ccsidr; +}