From patchwork Mon Aug 18 09:58:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 4734931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 145C09F377 for ; Mon, 18 Aug 2014 10:10:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 091822010C for ; Mon, 18 Aug 2014 10:10:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30E372011E for ; Mon, 18 Aug 2014 10:10:37 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XJJie-00041o-5h; Mon, 18 Aug 2014 09:59:16 +0000 Received: from regular1.263xmail.com ([211.150.99.140]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XJJiZ-0003xp-JQ for linux-arm-kernel@lists.infradead.org; Mon, 18 Aug 2014 09:59:14 +0000 Received: from kever.yang?rock-chips.com (unknown [192.168.167.128]) by regular1.263xmail.com (Postfix) with SMTP id AC6563F9A; Mon, 18 Aug 2014 17:58:36 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ABS-CHECKED: 4 X-KSVirus-check: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 5BC841F85D; Mon, 18 Aug 2014 17:58:22 +0800 (CST) X-RL-SENDER: kever.yang@rock-chips.com X-FST-TO: linux@arm.linux.org.uk X-SENDER-IP: 127.0.0.1 X-LOGIN-NAME: kever.yang@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: yk@rock-chips.com X-DNS-TYPE: 1 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) whith ESMTP id 23458I9XP4R; Mon, 18 Aug 2014 17:58:22 +0800 (CST) From: Kever Yang To: Russell King Subject: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 Date: Mon, 18 Aug 2014 17:58:09 +0800 Message-Id: <1408355889-4176-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140818_025911_955701_39BE8B5F X-CRM114-Status: GOOD ( 10.91 ) X-Spam-Score: -0.0 (/) Cc: huangtao@rock-chips.com, addy.ke@rock-chips.com, hj@rock-chips.com, Jonathan Austin , Nicolas Pitre , Will Deacon , linux-kernel@vger.kernel.org, Kever Yang , Mahesh Sivasubramanian , Marc Carino , xjq@rock-chips.com, Gregory CLEMENT , cf@rock-chips.com, Shawn Guo , Ben Dooks , linux-arm-kernel@lists.infradead.org, heiko@sntech.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Huang Tao On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an UNPREDICTABLE STR or STM instruction. This workaround setting bit[12] of the Feature Register prevents the erratum. This bit disables an optimisation applied to a sequence of 2 instructions that use opposing condition codes. Signed-off-by: Huang Tao Signed-off-by: Kever Yang --- arch/arm/Kconfig | 13 +++++++++++++ arch/arm/mm/proc-v7.S | 15 ++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 32cbbd5..4545835 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1245,6 +1245,19 @@ config ARM_ERRATA_773022 loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum. +config ARM_ERRATA_818325 + bool "ARM errata: Execution of an UNPREDICTABLE STR or STM instruction might deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 818325 Cortex-A12 + (r0p0..r0p1-00lac0-rc11) erratum. When a CPU executes a sequence of + two conditional store instructions with opposite condition code and + updating the same register, the system might enter a deadlock if the + second conditional instruction is an UNPREDICTABLE STR or STM + instruction. This workaround setting bit[12] of the Feature Register + prevents the erratum. This bit disables an optimisation applied to a + sequence of 2 instructions that use opposing condition codes. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b5d67db..5ffdf97 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -408,7 +408,20 @@ __v7_setup: mcrle p15, 0, r10, c1, c0, 1 @ write aux control register #endif -4: mov r10, #0 + /* Cortex-A12 Errata */ +4: ldr r10, =0x00000c0d @ Cortex-A12 primary part number + teq r0, r10 + bne 5f +#ifdef CONFIG_ARM_ERRATA_818325 + teq r6, #0x00 @ present in r0p0 + teqne r6, #0x01 @ present in r0p1-00lac0-rc11 + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 12 @ set bit #12 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register + isb +#endif + +5: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs