From patchwork Mon Aug 18 17:08:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 4738151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 10AADC0338 for ; Mon, 18 Aug 2014 17:12:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1060A20120 for ; Mon, 18 Aug 2014 17:12:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13FE520136 for ; Mon, 18 Aug 2014 17:12:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XJQQc-0002qf-J4; Mon, 18 Aug 2014 17:09:06 +0000 Received: from mail-qa0-f74.google.com ([209.85.216.74]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XJQQM-0002aU-Vi for linux-arm-kernel@lists.infradead.org; Mon, 18 Aug 2014 17:08:51 +0000 Received: by mail-qa0-f74.google.com with SMTP id j15so631452qaq.1 for ; Mon, 18 Aug 2014 10:08:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xrSdMcokJjpq3IaVFhF4qIOwEtUEKeKczD7ScbrHwkg=; b=Q5WZk5mhhJeylasmRZUi/UNYul+zgkoCiKAnR2E4VK2Wi7U0E9SmA56xS1JMqHqKSc LmaWYZccI1N17fuBme1Rypha8nZjGH7IBVT17sL/SyQwUQik7Z87LKAvtO3BDI1gUIzM NuLyspdUYsw62Hj2SplwNRBJVM6Y4wXaIaTqc92+tkRXyypHFtUlg5G6dBwJA5ioahUR B0EAHejaBZZMJaS4kezCnmkRdVGV+ZYV5MipJfJRxT6PRtnt/sLXupOrdnQPo2knx0Hp m5Ucqzhr2QXtjjKEXiF7vcntBCdpARvChv3rCPSVR+3clKF/7FRZ9bJ3omqu09Hb1cJA LRRQ== X-Gm-Message-State: ALoCoQk9WcY2T5I+xdsL7avf3rkMJDbiqVchqkNc27xZCK8numV0R3PRipcmb8RKal7zuwAj3OTb X-Received: by 10.52.145.161 with SMTP id sv1mr4556716vdb.7.1408381710828; Mon, 18 Aug 2014 10:08:30 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id v20si68685yhe.2.2014.08.18.10.08.30 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Aug 2014 10:08:30 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.65.70]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 8753731C5AE; Mon, 18 Aug 2014 10:08:30 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 4B224220C35; Mon, 18 Aug 2014 10:08:30 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , linux-tegra@vger.kernel.org Subject: [PATCH v2 3/9] of: Update Tegra XUSB pad controller binding for USB Date: Mon, 18 Aug 2014 10:08:19 -0700 Message-Id: <1408381705-3623-4-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1408381705-3623-1-git-send-email-abrestic@chromium.org> References: <1408381705-3623-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140818_100851_166391_49CA0465 X-CRM114-Status: GOOD ( 14.58 ) X-Spam-Score: -1.4 (-) Cc: Mark Rutland , devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Russell King , Mathias Nyman , Pawel Moll , Ian Campbell , Andrew Bresticker , Greg Kroah-Hartman , Linus Walleij , Jassi Brar , linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Rob Herring , Alan Stern , linux-arm-kernel@lists.infradead.org, Kumar Gala , Grant Likely , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new bindings used for USB support by the Tegra XUSB pad controller. This includes additional PHY types, USB-specific pinconfig properties, etc. Signed-off-by: Andrew Bresticker --- Changes from v1: - Updated to use common mailbox bindings. - Made USB3 port-to-lane mappins a top-level binding rather than a pinconfig binding. - Add #defines for the padctl lanes. --- .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 52 ++++++++++++++++++++-- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 20 +++++++++ 2 files changed, 68 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt index 2f9c0bd..606a5db 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt @@ -21,6 +21,16 @@ Required properties: - padctl - #phy-cells: Should be 1. The specifier is the index of the PHY to reference. See for the list of valid values. +- mboxes: Must contain an entry for the XUSB PHY mailbox channel. + See ../mailbox/mailbox.txt for details. + +Optional properties: +------------------- +- vbus-otg-{0,1,2}-supply: VBUS regulator for the corresponding UTMI pad. +- vddio-hsic-supply: VDDIO regulator for the HSIC pads. +- nvidia,usb3-port-{0,1}-lane: PCIe/SATA lane to which the corresponding USB3 + port is mapped. See for the list + of valid values. Lane muxing: ------------ @@ -50,6 +60,15 @@ Optional properties: pin or group should be assigned to. Valid values for function names are listed below. - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) +- nvidia,usb2-port-num: USB2 port (0, 1, or 2) to which the lane is mapped. +- nvidia,hsic-strobe-trim: HSIC strobe trimmer value. +- nvidia,hsic-rx-strobe-trim: HSIC RX strobe trimmer value. +- nvidia,hsic-rx-data-trim: HSIC RX data trimmer value. +- nvidia,hsic-tx-rtune-n: HSIC TX RTUNEN value. +- nvidia,hsic-tx-rtune-p: HSIC TX RTUNEP value. +- nvidia,hsic-tx-slew-n: HSIC TX SLEWN value. +- nvidia,hsic-tx-slew-p: HSIC TX SLEWP value. +- nvidia,hsic-auto-term: Enables HSIC AUTO_TERM. (0: no, 1: yes) Note that not all of these properties are valid for all lanes. Lanes can be divided into three groups: @@ -58,18 +77,22 @@ divided into three groups: Valid functions for this group are: "snps", "xusb", "uart", "rsvd". - The nvidia,iddq property does not apply to this group. + None of the other properties apply to this group. - ulpi-0, hsic-0, hsic-1: Valid functions for this group are: "snps", "xusb". - The nvidia,iddq property does not apply to this group. + The nvidia,hsic-* properties apply only to the pins hsic-{0,1} when + the function is xusb. - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". + The nvidia,usb2-port-num property only applies and is required when + the function is usb3. + Example: ======== @@ -82,6 +105,7 @@ SoC file extract: reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; + mboxes = <&mbox TEGRA_XUSB_MBOX_CHAN_PHY>; #phy-cells = <1>; }; @@ -100,15 +124,35 @@ Board file extract: ... + usb@0,70090000 { + ... + + phys = <&padctl 5>, <&padctl 6>, <&padctl 7>; + phy-names = "utmi-1", "utmi-2", "usb3-0"; + + ... + } + + ... + padctl: padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; + nvidia,usb3-port-0-lane = ; + vbus-otg-2-supply = <&vdd_usb3_vbus>; + padctl_default: pinmux { - usb3 { - nvidia,lanes = "pcie-0", "pcie-1"; + otg { + nvidia,lanes = "otg-1", "otg-2"; + nvidia,function = "xusb"; + }; + + usb3p0 { + nvidia,lanes = "pcie-0"; nvidia,function = "usb3"; nvidia,iddq = <0>; + nvidia,usb2-port-num = <2>; }; pcie { diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h index 914d56d..17b1aab 100644 --- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h @@ -3,5 +3,25 @@ #define TEGRA_XUSB_PADCTL_PCIE 0 #define TEGRA_XUSB_PADCTL_SATA 1 +#define TEGRA_XUSB_PADCTL_USB3_P0 2 +#define TEGRA_XUSB_PADCTL_USB3_P1 3 +#define TEGRA_XUSB_PADCTL_UTMI_P0 4 +#define TEGRA_XUSB_PADCTL_UTMI_P1 5 +#define TEGRA_XUSB_PADCTL_UTMI_P2 6 +#define TEGRA_XUSB_PADCTL_HSIC_P0 7 +#define TEGRA_XUSB_PADCTL_HSIC_P1 8 + +#define TEGRA_XUSB_PADCTL_PIN_OTG_0 0 +#define TEGRA_XUSB_PADCTL_PIN_OTG_1 1 +#define TEGRA_XUSB_PADCTL_PIN_OTG_2 2 +#define TEGRA_XUSB_PADCTL_PIN_ULPI_0 3 +#define TEGRA_XUSB_PADCTL_PIN_HSIC_0 4 +#define TEGRA_XUSB_PADCTL_PIN_HSIC_1 5 +#define TEGRA_XUSB_PADCTL_PIN_PCIE_0 6 +#define TEGRA_XUSB_PADCTL_PIN_PCIE_1 7 +#define TEGRA_XUSB_PADCTL_PIN_PCIE_2 8 +#define TEGRA_XUSB_PADCTL_PIN_PCIE_3 9 +#define TEGRA_XUSB_PADCTL_PIN_PCIE_4 10 +#define TEGRA_XUSB_PADCTL_PIN_SATA_0 11 #endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */