From patchwork Mon Aug 25 00:51:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 4773461 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2E6B69F38D for ; Mon, 25 Aug 2014 10:07:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4111720107 for ; Mon, 25 Aug 2014 10:07:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5FC3920103 for ; Mon, 25 Aug 2014 10:07:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XLr6k-0008QB-1F; Mon, 25 Aug 2014 10:02:38 +0000 Received: from mezzanine.sirena.org.uk ([2400:8900::f03c:91ff:fedb:4f4]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XLr6h-000847-8k for linux-arm-kernel@lists.infradead.org; Mon, 25 Aug 2014 10:02:35 +0000 Received: from cpc11-sgyl31-2-0-cust672.sgyl.cable.virginm.net ([94.175.94.161] helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1XLr6H-0005AS-74; Mon, 25 Aug 2014 10:02:13 +0000 Received: from broonie by finisterre with local (Exim 4.84_RC1) (envelope-from ) id 1XLiVT-00082L-3S; Sun, 24 Aug 2014 19:51:35 -0500 From: Mark Brown To: Anton Vorontsov Date: Sun, 24 Aug 2014 19:51:34 -0500 Message-Id: <1408927894-30858-1-git-send-email-broonie@kernel.org> X-Mailer: git-send-email 2.1.0.rc1 X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Subject: [PATCH] ARM: cns3xxx: Don't allocate PCI addresses on stack X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140825_030235_428389_2CD1ADE4 X-CRM114-Status: GOOD ( 14.01 ) X-Spam-Score: -0.0 (/) Cc: linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Mark Brown X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mark Brown The cns3xxx PCIe code allocates a PCI bus structure on the stack, causing warnings due to the excessibe size of the resulting stack frame: arch/arm/mach-cns3xxx/pcie.c:311:1: warning: the frame size of 1072 bytes is larger than 1024 bytes [-Wframe-larger-than=] Avoid this by dynamically allocating the structure, though I am not convinced that we should be locally creating the struct pci_bus in the first place. Signed-off-by: Mark Brown --- arch/arm/mach-cns3xxx/pcie.c | 49 ++++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 413134c..67964f9 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "cns3xxx.h" #include "core.h" @@ -266,11 +267,7 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) struct pci_sys_data sd = { .domain = port, }; - struct pci_bus bus = { - .number = 0, - .ops = &cns3xxx_pcie_ops, - .sysdata = &sd, - }; + struct pci_bus *bus; u16 mem_base = cnspci->res_mem.start >> 16; u16 mem_limit = cnspci->res_mem.end >> 16; u16 io_base = cnspci->res_io.start >> 16; @@ -280,34 +277,46 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) u16 pos; u16 dc; - pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0); - pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1); - pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1); + bus = kzalloc(sizeof(*bus), GFP_KERNEL); + if (!bus) + return; + + bus->number = 0; + bus->ops = &cns3xxx_pcie_ops; + bus->sysdata = &sd; - pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8); - pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8); - pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8); + pci_bus_write_config_byte(bus, devfn, PCI_PRIMARY_BUS, 0); + pci_bus_write_config_byte(bus, devfn, PCI_SECONDARY_BUS, 1); + pci_bus_write_config_byte(bus, devfn, PCI_SUBORDINATE_BUS, 1); - pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base); - pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit); - pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base); - pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit); + pci_bus_read_config_byte(bus, devfn, PCI_PRIMARY_BUS, &tmp8); + pci_bus_read_config_byte(bus, devfn, PCI_SECONDARY_BUS, &tmp8); + pci_bus_read_config_byte(bus, devfn, PCI_SUBORDINATE_BUS, &tmp8); - if (!cnspci->linked) + pci_bus_write_config_word(bus, devfn, PCI_MEMORY_BASE, mem_base); + pci_bus_write_config_word(bus, devfn, PCI_MEMORY_LIMIT, mem_limit); + pci_bus_write_config_word(bus, devfn, PCI_IO_BASE_UPPER16, io_base); + pci_bus_write_config_word(bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit); + + if (!cnspci->linked) { + kfree(bus); return; + } /* Set Device Max_Read_Request_Size to 128 byte */ devfn = PCI_DEVFN(1, 0); - pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); - pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); + pos = pci_bus_find_capability(bus, devfn, PCI_CAP_ID_EXP); + pci_bus_read_config_word(bus, devfn, pos + PCI_EXP_DEVCTL, &dc); dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ - pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); - pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); + pci_bus_write_config_word(bus, devfn, pos + PCI_EXP_DEVCTL, dc); + pci_bus_read_config_word(bus, devfn, pos + PCI_EXP_DEVCTL, &dc); if (!(dc & (0x3 << 12))) pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n"); /* Disable PCIe0 Interrupt Mask INTA to INTD */ __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port)); + + kfree(bus); } static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,